ufs: Active Power Mode - configuring bActiveICCLevel

[pandora-kernel.git] / drivers / scsi / ufs / ufs.h

diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
index f42d1ce..4ca99ed 100644 (file)
--- a/drivers/scsi/ufs/ufs.h
+++ b/drivers/scsi/ufs/ufs.h
@@ -41,7 +41,8 @@
 
 #define MAX_CDB_SIZE   16
 #define GENERAL_UPIU_REQUEST_SIZE 32
-#define QUERY_DESC_MAX_SIZE       256
+#define QUERY_DESC_MAX_SIZE       255
+#define QUERY_DESC_MIN_SIZE       2
 #define QUERY_OSF_SIZE            (GENERAL_UPIU_REQUEST_SIZE - \
                                        (sizeof(struct utp_upiu_header)))
 
@@ -49,6 +50,8 @@
                        cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
                         (byte1 << 8) | (byte0))
 
+#define UFS_UPIU_MAX_GENERAL_LUN       8
+
 /*
  * UFS Protocol Information Unit related definitions
  */
@@ -112,11 +115,91 @@ enum flag_idn {
 
 /* Attribute idn for Query requests */
 enum attr_idn {
+       QUERY_ATTR_IDN_ACTIVE_ICC_LVL   = 0x03,
        QUERY_ATTR_IDN_BKOPS_STATUS     = 0x05,
        QUERY_ATTR_IDN_EE_CONTROL       = 0x0D,
        QUERY_ATTR_IDN_EE_STATUS        = 0x0E,
 };
 
+/* Descriptor idn for Query requests */
+enum desc_idn {
+       QUERY_DESC_IDN_DEVICE           = 0x0,
+       QUERY_DESC_IDN_CONFIGURAION     = 0x1,
+       QUERY_DESC_IDN_UNIT             = 0x2,
+       QUERY_DESC_IDN_RFU_0            = 0x3,
+       QUERY_DESC_IDN_INTERCONNECT     = 0x4,
+       QUERY_DESC_IDN_STRING           = 0x5,
+       QUERY_DESC_IDN_RFU_1            = 0x6,
+       QUERY_DESC_IDN_GEOMETRY         = 0x7,
+       QUERY_DESC_IDN_POWER            = 0x8,
+       QUERY_DESC_IDN_MAX,
+};
+
+enum desc_header_offset {
+       QUERY_DESC_LENGTH_OFFSET        = 0x00,
+       QUERY_DESC_DESC_TYPE_OFFSET     = 0x01,
+};
+
+enum ufs_desc_max_size {
+       QUERY_DESC_DEVICE_MAX_SIZE              = 0x1F,
+       QUERY_DESC_CONFIGURAION_MAX_SIZE        = 0x90,
+       QUERY_DESC_UNIT_MAX_SIZE                = 0x23,
+       QUERY_DESC_INTERCONNECT_MAX_SIZE        = 0x06,
+       /*
+        * Max. 126 UNICODE characters (2 bytes per character) plus 2 bytes
+        * of descriptor header.
+        */
+       QUERY_DESC_STRING_MAX_SIZE              = 0xFE,
+       QUERY_DESC_GEOMETRY_MAZ_SIZE            = 0x44,
+       QUERY_DESC_POWER_MAX_SIZE               = 0x62,
+       QUERY_DESC_RFU_MAX_SIZE                 = 0x00,
+};
+
+/* Unit descriptor parameters offsets in bytes*/
+enum unit_desc_param {
+       UNIT_DESC_PARAM_LEN                     = 0x0,
+       UNIT_DESC_PARAM_TYPE                    = 0x1,
+       UNIT_DESC_PARAM_UNIT_INDEX              = 0x2,
+       UNIT_DESC_PARAM_LU_ENABLE               = 0x3,
+       UNIT_DESC_PARAM_BOOT_LUN_ID             = 0x4,
+       UNIT_DESC_PARAM_LU_WR_PROTECT           = 0x5,
+       UNIT_DESC_PARAM_LU_Q_DEPTH              = 0x6,
+       UNIT_DESC_PARAM_MEM_TYPE                = 0x8,
+       UNIT_DESC_PARAM_DATA_RELIABILITY        = 0x9,
+       UNIT_DESC_PARAM_LOGICAL_BLK_SIZE        = 0xA,
+       UNIT_DESC_PARAM_LOGICAL_BLK_COUNT       = 0xB,
+       UNIT_DESC_PARAM_ERASE_BLK_SIZE          = 0x13,
+       UNIT_DESC_PARAM_PROVISIONING_TYPE       = 0x17,
+       UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT        = 0x18,
+       UNIT_DESC_PARAM_CTX_CAPABILITIES        = 0x20,
+       UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1      = 0x22,
+};
+
+/* bActiveICCLevel parameter current units */
+enum {
+       UFSHCD_NANO_AMP         = 0,
+       UFSHCD_MICRO_AMP        = 1,
+       UFSHCD_MILI_AMP         = 2,
+       UFSHCD_AMP              = 3,
+};
+
+#define POWER_DESC_MAX_SIZE                    0x62
+#define POWER_DESC_MAX_ACTV_ICC_LVLS           16
+
+/* Attribute  bActiveICCLevel parameter bit masks definitions */
+#define ATTR_ICC_LVL_UNIT_OFFSET       14
+#define ATTR_ICC_LVL_UNIT_MASK         (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
+#define ATTR_ICC_LVL_VALUE_MASK                0x3FF
+
+/* Power descriptor parameters offsets in bytes */
+enum power_desc_param_offset {
+       PWR_DESC_LEN                    = 0x0,
+       PWR_DESC_TYPE                   = 0x1,
+       PWR_DESC_ACTIVE_LVLS_VCC_0      = 0x2,
+       PWR_DESC_ACTIVE_LVLS_VCCQ_0     = 0x22,
+       PWR_DESC_ACTIVE_LVLS_VCCQ2_0    = 0x42,
+};
+
 /* Exception event mask values */
 enum {
        MASK_EE_STATUS          = 0xFFFF,
@@ -326,4 +409,30 @@ struct ufs_query_res {
        struct utp_upiu_query upiu_res;
 };
 
+#define UFS_VREG_VCC_MIN_UV       2700000 /* uV */
+#define UFS_VREG_VCC_MAX_UV       3600000 /* uV */
+#define UFS_VREG_VCC_1P8_MIN_UV    1700000 /* uV */
+#define UFS_VREG_VCC_1P8_MAX_UV    1950000 /* uV */
+#define UFS_VREG_VCCQ_MIN_UV      1100000 /* uV */
+#define UFS_VREG_VCCQ_MAX_UV      1300000 /* uV */
+#define UFS_VREG_VCCQ2_MIN_UV     1650000 /* uV */
+#define UFS_VREG_VCCQ2_MAX_UV     1950000 /* uV */
+
+struct ufs_vreg {
+       struct regulator *reg;
+       const char *name;
+       bool enabled;
+       int min_uV;
+       int max_uV;
+       int min_uA;
+       int max_uA;
+};
+
+struct ufs_vreg_info {
+       struct ufs_vreg *vcc;
+       struct ufs_vreg *vccq;
+       struct ufs_vreg *vccq2;
+       struct ufs_vreg *vdd_hba;
+};
+
 #endif /* End of Header */