[SCSI] mvsas: update comments

[pandora-kernel.git] / drivers / scsi / mvsas / mv_94xx.h

diff --git a/drivers/scsi/mvsas/mv_94xx.h b/drivers/scsi/mvsas/mv_94xx.h
index 8835bef..8f7eb4f 100644 (file)
--- a/drivers/scsi/mvsas/mv_94xx.h
+++ b/drivers/scsi/mvsas/mv_94xx.h
@@ -30,6 +30,14 @@
 
 #define MAX_LINK_RATE          SAS_LINK_RATE_6_0_GBPS
 
+enum VANIR_REVISION_ID {
+       VANIR_A0_REV            = 0xA0,
+       VANIR_B0_REV            = 0x01,
+       VANIR_C0_REV            = 0x02,
+       VANIR_C1_REV            = 0x03,
+       VANIR_C2_REV            = 0xC2,
+};
+
 enum hw_registers {
        MVS_GBL_CTL             = 0x04,  /* global control */
        MVS_GBL_INT_STAT        = 0x00,  /* global irq status */
@@ -101,6 +109,7 @@ enum hw_registers {
        MVS_P4_VSR_DATA         = 0x254, /* phy4 VSR data */
        MVS_PA_VSR_ADDR         = 0x290, /* All port VSR addr */
        MVS_PA_VSR_PORT         = 0x294, /* All port VSR data */
+       MVS_COMMAND_ACTIVE      = 0x300,
 };
 
 enum pci_cfg_registers {
@@ -112,26 +121,29 @@ enum pci_cfg_registers {
 
 /*  SAS/SATA Vendor Specific Port Registers */
 enum sas_sata_vsp_regs {
-       VSR_PHY_STAT            = 0x00 * 4, /* Phy Status */
-       VSR_PHY_MODE1           = 0x01 * 4, /* phy tx */
-       VSR_PHY_MODE2           = 0x02 * 4, /* tx scc */
-       VSR_PHY_MODE3           = 0x03 * 4, /* pll */
-       VSR_PHY_MODE4           = 0x04 * 4, /* VCO */
-       VSR_PHY_MODE5           = 0x05 * 4, /* Rx */
-       VSR_PHY_MODE6           = 0x06 * 4, /* CDR */
-       VSR_PHY_MODE7           = 0x07 * 4, /* Impedance */
-       VSR_PHY_MODE8           = 0x08 * 4, /* Voltage */
-       VSR_PHY_MODE9           = 0x09 * 4, /* Test */
-       VSR_PHY_MODE10          = 0x0A * 4, /* Power */
-       VSR_PHY_MODE11          = 0x0B * 4, /* Phy Mode */
-       VSR_PHY_VS0             = 0x0C * 4, /* Vednor Specific 0 */
-       VSR_PHY_VS1             = 0x0D * 4, /* Vednor Specific 1 */
+       VSR_PHY_STAT            = 0x00 * 4, /* Phy Interrupt Status */
+       VSR_PHY_MODE1           = 0x01 * 4, /* phy Interrupt Enable */
+       VSR_PHY_MODE2           = 0x02 * 4, /* Phy Configuration */
+       VSR_PHY_MODE3           = 0x03 * 4, /* Phy Status */
+       VSR_PHY_MODE4           = 0x04 * 4, /* Phy Counter 0 */
+       VSR_PHY_MODE5           = 0x05 * 4, /* Phy Counter 1 */
+       VSR_PHY_MODE6           = 0x06 * 4, /* Event Counter Control */
+       VSR_PHY_MODE7           = 0x07 * 4, /* Event Counter Select */
+       VSR_PHY_MODE8           = 0x08 * 4, /* Event Counter 0 */
+       VSR_PHY_MODE9           = 0x09 * 4, /* Event Counter 1 */
+       VSR_PHY_MODE10          = 0x0A * 4, /* Event Counter 2 */
+       VSR_PHY_MODE11          = 0x0B * 4, /* Event Counter 3 */
+       VSR_PHY_ACT_LED         = 0x0C * 4, /* Activity LED control */
+
+       VSR_PHY_FFE_CONTROL     = 0x10C,
+       VSR_PHY_DFE_UPDATE_CRTL = 0x110,
+       VSR_REF_CLOCK_CRTL      = 0x1A0,
 };
 
 enum chip_register_bits {
        PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
-       PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 8),
-       PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (12),
+       PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0x7 << 12),
+       PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
        PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
                        (0x3 << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
 };
@@ -169,22 +181,75 @@ enum pci_interrupt_cause {
        IRQ_PCIE_ERR                   = (1 << 31),
 };
 
+union reg_phy_cfg {
+       u32 v;
+       struct {
+               u32 phy_reset:1;
+               u32 sas_support:1;
+               u32 sata_support:1;
+               u32 sata_host_mode:1;
+               /*
+                * bit 2: 6Gbps support
+                * bit 1: 3Gbps support
+                * bit 0: 1.5Gbps support
+                */
+               u32 speed_support:3;
+               u32 snw_3_support:1;
+               u32 tx_lnk_parity:1;
+               /*
+                * bit 5: G1 (1.5Gbps) Without SSC
+                * bit 4: G1 (1.5Gbps) with SSC
+                * bit 3: G2 (3.0Gbps) Without SSC
+                * bit 2: G2 (3.0Gbps) with SSC
+                * bit 1: G3 (6.0Gbps) without SSC
+                * bit 0: G3 (6.0Gbps) with SSC
+                */
+               u32 tx_spt_phs_lnk_rate:6;
+               /* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
+               u32 tx_lgcl_lnk_rate:4;
+               u32 tx_ssc_type:1;
+               u32 sata_spin_up_spt:1;
+               u32 sata_spin_up_en:1;
+               u32 bypass_oob:1;
+               u32 disable_phy:1;
+               u32 rsvd:8;
+       } u;
+};
+
 #define MAX_SG_ENTRY           255
 
 struct mvs_prd_imt {
+#ifndef __BIG_ENDIAN
        __le32                  len:22;
        u8                      _r_a:2;
        u8                      misc_ctl:4;
        u8                      inter_sel:4;
+#else
+       u32                     inter_sel:4;
+       u32                     misc_ctl:4;
+       u32                     _r_a:2;
+       u32                     len:22;
+#endif
 };
 
 struct mvs_prd {
        /* 64-bit buffer address */
        __le64                  addr;
        /* 22-bit length */
-       struct mvs_prd_imt      im_len;
+       __le32                  im_len;
 } __attribute__ ((packed));
 
+/*
+ * these registers are accessed through port vendor
+ * specific address/data registers
+ */
+enum sas_sata_phy_regs {
+       GENERATION_1_SETTING            = 0x118,
+       GENERATION_1_2_SETTING          = 0x11C,
+       GENERATION_2_3_SETTING          = 0x120,
+       GENERATION_3_4_SETTING          = 0x124,
+};
+
 #define SPI_CTRL_REG_94XX              0xc800
 #define SPI_ADDR_REG_94XX              0xc804
 #define SPI_WR_DATA_REG_94XX         0xc808