iwlagn: all function iwl-io.c receive iwl_bus

[pandora-kernel.git] / drivers / net / wireless / iwlwifi / iwl-trans-tx-pcie.c

diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
index 835e3ed..3105409 100644 (file)
--- a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
@@ -96,7 +96,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 
        if (priv->cfg->base_params->shadow_reg_enable) {
                /* shadow register enabled */
-               iwl_write32(priv, HBUS_TARG_WRPTR,
+               iwl_write32(bus(priv), HBUS_TARG_WRPTR,
                            txq->q.write_ptr | (txq_id << 8));
        } else {
                /* if we're trying to save power */
@@ -104,18 +104,18 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
                        /* wake up nic if it's powered down ...
                         * uCode will wake up, and interrupt us again, so next
                         * time we'll skip this part. */
-                       reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
+                       reg = iwl_read32(bus(priv), CSR_UCODE_DRV_GP1);
 
                        if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
                                IWL_DEBUG_INFO(priv,
                                        "Tx queue %d requesting wakeup,"
                                        " GP1 = 0x%x\n", txq_id, reg);
-                               iwl_set_bit(priv, CSR_GP_CNTRL,
+                               iwl_set_bit(bus(priv), CSR_GP_CNTRL,
                                        CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
                                return;
                        }
 
-                       iwl_write_direct32(priv, HBUS_TARG_WRPTR,
+                       iwl_write_direct32(bus(priv), HBUS_TARG_WRPTR,
                                     txq->q.write_ptr | (txq_id << 8));
 
                /*
@@ -124,7 +124,7 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
                 * trying to tx (during RFKILL, we're not trying to tx).
                 */
                } else
-                       iwl_write32(priv, HBUS_TARG_WRPTR,
+                       iwl_write32(bus(priv), HBUS_TARG_WRPTR,
                                    txq->q.write_ptr | (txq_id << 8));
        }
        txq->need_update = 0;
@@ -374,14 +374,14 @@ static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
        tbl_dw_addr = trans_pcie->scd_base_addr +
                        SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 
-       tbl_dw = iwl_read_targ_mem(priv(trans), tbl_dw_addr);
+       tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
 
        if (txq_id & 0x1)
                tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
        else
                tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 
-       iwl_write_targ_mem(priv(trans), tbl_dw_addr, tbl_dw);
+       iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
 
        return 0;
 }
@@ -390,7 +390,7 @@ static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 {
        /* Simply stop the queue, but don't change any configuration;
         * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
-       iwl_write_prph(priv(trans),
+       iwl_write_prph(bus(trans),
                SCD_QUEUE_STATUS_BITS(txq_id),
                (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
                (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
@@ -399,9 +399,9 @@ static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
                                int txq_id, u32 index)
 {
-       iwl_write_direct32(priv(trans), HBUS_TARG_WRPTR,
+       iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
                        (index & 0xff) | (txq_id << 8));
-       iwl_write_prph(priv(trans), SCD_QUEUE_RDPTR(txq_id), index);
+       iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
 }
 
 void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
@@ -411,7 +411,7 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
        int txq_id = txq->q.id;
        int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 
-       iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
+       iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
                        (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
                        (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
                        (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -459,10 +459,10 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
        iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 
        /* Set this queue as a chain-building queue */
-       iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
+       iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
 
        /* enable aggregations for the queue */
-       iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
+       iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
 
        /* Place first TFD at index corresponding to start sequence number.
         * Assumes that ssn_idx is valid (!= 0xFFF) */
@@ -471,7 +471,7 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
        iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
 
        /* Set up Tx window size and frame limit for this queue */
-       iwl_write_targ_mem(priv, trans_pcie->scd_base_addr +
+       iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
                        SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
                        sizeof(u32),
                        ((frame_limit <<
@@ -481,7 +481,7 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
                        SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
                        SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 
-       iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
+       iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
 
        /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
        iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
@@ -509,14 +509,14 @@ int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 
        iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 
-       iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
+       iwl_clear_bits_prph(bus(priv), SCD_AGGR_SEL, (1 << txq_id));
 
        priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
        priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
        /* supposes that ssn_idx is valid (!= 0xFFF) */
        iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
 
-       iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
+       iwl_clear_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
        iwl_txq_ctx_deactivate(priv, txq_id);
        iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);