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atheros: add ieee80211_hw to ath_common
[pandora-kernel.git] / drivers / net / wireless / ath / ath9k / calib.c
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 3234995..bdd4a19 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -26,7 +26,7 @@
 static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
 {
        if (nf > ATH9K_NF_TOO_LOW) {
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "noise floor value detected (%d) is "
                        "lower than what we think is a "
                        "reasonable value (%d)\n",
@@ -98,7 +98,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+       DPRINTF(ah, ATH_DBG_CALIBRATE,
                "NF calibrated [ctl] [chain 0] is %d\n", nf);
        nfarray[0] = nf;
 
@@ -112,7 +112,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
 
                if (nf & 0x100)
                        nf = 0 - ((nf ^ 0x1ff) + 1);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "NF calibrated [ctl] [chain 1] is %d\n", nf);
                nfarray[1] = nf;
 
@@ -121,7 +121,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
                                        AR_PHY_CH2_MINCCA_PWR);
                        if (nf & 0x100)
                                nf = 0 - ((nf ^ 0x1ff) + 1);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "NF calibrated [ctl] [chain 2] is %d\n", nf);
                        nfarray[2] = nf;
                }
@@ -136,7 +136,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
 
        if (nf & 0x100)
                nf = 0 - ((nf ^ 0x1ff) + 1);
-       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+       DPRINTF(ah, ATH_DBG_CALIBRATE,
                "NF calibrated [ext] [chain 0] is %d\n", nf);
        nfarray[3] = nf;
 
@@ -150,7 +150,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
 
                if (nf & 0x100)
                        nf = 0 - ((nf ^ 0x1ff) + 1);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "NF calibrated [ext] [chain 1] is %d\n", nf);
                nfarray[4] = nf;
 
@@ -159,7 +159,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
                                        AR_PHY_CH2_EXT_MINCCA_PWR);
                        if (nf & 0x100)
                                nf = 0 - ((nf ^ 0x1ff) + 1);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "NF calibrated [ext] [chain 2] is %d\n", nf);
                        nfarray[5] = nf;
                }
@@ -195,22 +195,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
        switch (currCal->calData->calType) {
        case IQ_MISMATCH_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "starting IQ Mismatch Calibration\n");
                break;
        case ADC_GAIN_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "starting ADC Gain Calibration\n");
                break;
        case ADC_DC_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "starting ADC DC Calibration\n");
                break;
        case ADC_DC_INIT_CAL:
                REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "starting Init ADC DC Calibration\n");
                break;
        }
@@ -278,7 +278,7 @@ static bool ath9k_hw_per_calibration(struct ath_hw *ah,
 static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
                                     enum ath9k_cal_types calType)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 
        switch (calType & ah->supp_cals) {
        case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
@@ -304,7 +304,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
                        REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                ah->totalIqCorrMeas[i] +=
                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
                        ah->cal_samples, i, ah->totalPowerMeasI[i],
                        ah->totalPowerMeasQ[i],
@@ -326,7 +326,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
                ah->totalAdcQEvenPhase[i] +=
                        REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
                        "oddq=0x%08x; evenq=0x%08x;\n",
                        ah->cal_samples, i,
@@ -351,7 +351,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
                ah->totalAdcDcOffsetQEvenPhase[i] +=
                        (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
                        "oddq=0x%08x; evenq=0x%08x;\n",
                        ah->cal_samples, i,
@@ -374,11 +374,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                powerMeasQ = ah->totalPowerMeasQ[i];
                iqCorrMeas = ah->totalIqCorrMeas[i];
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Starting IQ Cal and Correction for Chain %d\n",
                        i);
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
                        i, ah->totalIqCorrMeas[i]);
 
@@ -389,11 +389,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                        iqCorrNeg = 1;
                }
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+               DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
                        iqCorrNeg);
 
                iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
@@ -402,13 +402,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                if (powerMeasQ != 0) {
                        iCoff = iqCorrMeas / iCoffDenom;
                        qCoff = powerMeasI / qCoffDenom - 64;
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                        iCoff = iCoff & 0x3f;
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
                        if (iqCorrNeg == 0x0)
                                iCoff = 0x40 - iCoff;
@@ -418,7 +418,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                        else if (qCoff <= -16)
                                qCoff = 16;
 
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
                                i, iCoff, qCoff);
 
@@ -428,7 +428,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                        REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                      AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
                                      qCoff);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "IQ Cal and Correction done for Chain %d\n",
                                i);
                }
@@ -449,19 +449,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                qOddMeasOffset = ah->totalAdcQOddPhase[i];
                qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Starting ADC Gain Cal for Chain %d\n", i);
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
                        iOddMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_even_i = 0x%08x\n", i,
                        iEvenMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
                        qOddMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_even_q = 0x%08x\n", i,
                        qEvenMeasOffset);
 
@@ -473,10 +473,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                                ((qOddMeasOffset * 32) /
                                 qEvenMeasOffset) & 0x3f;
 
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "Chn %d gain_mismatch_i = 0x%08x\n", i,
                                iGainMismatch);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "Chn %d gain_mismatch_q = 0x%08x\n", i,
                                qGainMismatch);
 
@@ -485,7 +485,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                        val |= (qGainMismatch) | (iGainMismatch << 6);
                        REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "ADC Gain Cal done for Chain %d\n", i);
                }
        }
@@ -510,19 +510,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
                qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Starting ADC DC Offset Cal for Chain %d\n", i);
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_odd_i = %d\n", i,
                        iOddMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_even_i = %d\n", i,
                        iEvenMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_odd_q = %d\n", i,
                        qOddMeasOffset);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d pwr_meas_even_q = %d\n", i,
                        qEvenMeasOffset);
 
@@ -531,10 +531,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
                               numSamples) & 0x1ff;
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
                        iDcMismatch);
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
                        qDcMismatch);
 
@@ -543,7 +543,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                val |= (qDcMismatch << 12) | (iDcMismatch << 21);
                REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "ADC DC Offset Cal done for Chain %d\n", i);
        }
 
@@ -555,7 +555,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
 /* This is done for the currently configured channel */
 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
 {
-       struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
+       struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
        struct ath9k_cal_list *currCal = ah->cal_list_curr;
 
        if (!ah->curchan)
@@ -568,7 +568,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
                return true;
 
        if (currCal->calState != CAL_DONE) {
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "Calibration state incorrect, %d\n",
                        currCal->calState);
                return true;
@@ -577,7 +577,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
        if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
                return true;
 
-       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+       DPRINTF(ah, ATH_DBG_CALIBRATE,
                "Resetting Cal %d state for channel %u\n",
                currCal->calData->calType, conf->channel->center_freq);
 
@@ -609,14 +609,24 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
                AR_PHY_CH1_EXT_CCA,
                AR_PHY_CH2_EXT_CCA
        };
-       u8 chainmask;
+       u8 chainmask, rx_chain_status;
 
+       rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
        if (AR_SREV_9285(ah))
                chainmask = 0x9;
-       else if (AR_SREV_9280(ah) || AR_SREV_9287(ah))
-               chainmask = 0x1B;
-       else
-               chainmask = 0x3F;
+       else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
+               if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
+                       chainmask = 0x1B;
+               else
+                       chainmask = 0x09;
+       } else {
+               if (rx_chain_status & 0x4)
+                       chainmask = 0x3F;
+               else if (rx_chain_status & 0x2)
+                       chainmask = 0x1B;
+               else
+                       chainmask = 0x09;
+       }
 
        h = ah->nfCalHist;
 
@@ -662,7 +672,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
 
        chan->channelFlags &= (~CHANNEL_CW_INT);
        if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+               DPRINTF(ah, ATH_DBG_CALIBRATE,
                        "NF did not complete in calibration window\n");
                nf = 0;
                chan->rawNoiseFloor = nf;
@@ -672,7 +682,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
                nf = nfarray[0];
                if (getNoiseFloorThresh(ah, c->band, &nfThresh)
                    && nf > nfThresh) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "noise floor failed detected; "
                                "detected %d, threshold %d\n",
                                nf, nfThresh);
@@ -697,6 +707,8 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
                noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
        else if (AR_SREV_9285(ah))
                noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
+       else if (AR_SREV_9287(ah))
+               noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
        else
                noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
 
@@ -877,7 +889,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
                { 0x7838, 0 },
        };
 
-       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
+       DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 
        /* PA CAL is not needed for high power solution */
        if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -924,6 +936,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
                regVal |= (1 << (19 + i));
                REG_WRITE(ah, 0x7834, regVal);
                udelay(1);
+               regVal = REG_READ(ah, 0x7834);
                regVal &= (~(0x1 << (19 + i)));
                reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
                regVal |= (reg_field << (19 + i));
@@ -1036,7 +1049,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
                REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
                if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                  AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset "
+                       DPRINTF(ah, ATH_DBG_CALIBRATE, "offset "
                                "calibration failed to complete in "
                                "1ms; noisy ??\n");
                        return false;
@@ -1051,7 +1064,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
        REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
        if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                          0, AH_WAIT_TIMEOUT)) {
-               DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration "
+               DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration "
                                "failed to complete in 1ms; noisy ??\n");
                return false;
        }
@@ -1085,7 +1098,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                /* Poll for offset calibration complete */
                if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                                   0, AH_WAIT_TIMEOUT)) {
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "offset calibration failed to complete in 1ms; "
                                "noisy environment?\n");
                        return false;
@@ -1115,19 +1128,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
                        INIT_CAL(&ah->adcgain_caldata);
                        INSERT_CAL(ah, &ah->adcgain_caldata);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "enabling ADC Gain Calibration.\n");
                }
                if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
                        INIT_CAL(&ah->adcdc_caldata);
                        INSERT_CAL(ah, &ah->adcdc_caldata);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "enabling ADC DC Calibration.\n");
                }
                if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
                        INIT_CAL(&ah->iq_caldata);
                        INSERT_CAL(ah, &ah->iq_caldata);
-                       DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
+                       DPRINTF(ah, ATH_DBG_CALIBRATE,
                                "enabling IQ Calibration.\n");
                }
 
Pandora Kernel Repository