csr6 |= DMA_CONTROL_TTC_128;
writel(csr6, ioaddr + DMA_CONTROL);
-
- return;
}
static void dwmac100_dump_dma_regs(unsigned long ioaddr)
DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
CHIP_DBG(KERN_DEBUG "\t CSR21 (offset 0x%x): 0x%08x\n",
DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
- return;
}
/* DMA controller has two counters to track the number of
x->rx_missed_cntr += miss_f;
}
}
- return;
}
struct stmmac_dma_ops dwmac100_dma_ops = {