[SUNGEM]: PHY updates & pause fixes (#2)

[pandora-kernel.git] / drivers / net / smc91x.h

diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index c660e33..d2767e6 100644 (file)
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -195,6 +195,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define        SMC_IRQ_FLAGS (( \
                   machine_is_omap_h2() \
                || machine_is_omap_h3() \
+               || machine_is_omap_h4() \
                || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
        ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
 
@@ -237,7 +238,7 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
 #define SMC_CAN_USE_16BIT      1
 #define SMC_CAN_USE_32BIT      0
 
-#define SMC_inb(a, r)          inb((u32)a) + (r))
+#define SMC_inb(a, r)          inb(((u32)a) + (r))
 #define SMC_inw(a, r)          inw(((u32)a) + (r))
 #define SMC_outb(v, a, r)      outb(v, ((u32)a) + (r))
 #define SMC_outw(v, a, r)      outw(v, ((u32)a) + (r))
@@ -361,42 +362,6 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
 
 #define SMC_IRQ_FLAGS          (0)
 
-#elif  defined(CONFIG_ARCH_VERSATILE)
-
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
-
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
-
-#define SMC_IRQ_FLAGS          (0)
-
-#elif  defined(CONFIG_ARCH_VERSATILE)
-
-#define SMC_CAN_USE_8BIT       1
-#define SMC_CAN_USE_16BIT      1
-#define SMC_CAN_USE_32BIT      1
-#define SMC_NOWAIT             1
-
-#define SMC_inb(a, r)          readb((a) + (r))
-#define SMC_inw(a, r)          readw((a) + (r))
-#define SMC_inl(a, r)          readl((a) + (r))
-#define SMC_outb(v, a, r)      writeb(v, (a) + (r))
-#define SMC_outw(v, a, r)      writew(v, (a) + (r))
-#define SMC_outl(v, a, r)      writel(v, (a) + (r))
-#define SMC_insl(a, r, p, l)   readsl((a) + (r), p, l)
-#define SMC_outsl(a, r, p, l)  writesl((a) + (r), p, l)
-
-#define SMC_IRQ_FLAGS          (0)
-
 #else
 
 #define SMC_CAN_USE_8BIT       1
@@ -506,7 +471,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
 #endif
 
 static void
-smc_pxa_dma_irq(int dma, void *dummy, struct pt_regs *regs)
+smc_pxa_dma_irq(int dma, void *dummy)
 {
        DCSR(dma) = 0;
 }
@@ -1179,7 +1144,7 @@ static const char * chip_ids[ 16 ] =  {
                if (SMC_CAN_USE_32BIT) {                                \
                        void *__ptr = (p);                              \
                        int __len = (l);                                \
-                       void *__ioaddr = ioaddr;                        \
+                       void __iomem *__ioaddr = ioaddr;                \
                        if (__len >= 2 && (unsigned long)__ptr & 2) {   \
                                __len -= 2;                             \
                                SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
@@ -1203,7 +1168,7 @@ static const char * chip_ids[ 16 ] =  {
                if (SMC_CAN_USE_32BIT) {                                \
                        void *__ptr = (p);                              \
                        int __len = (l);                                \
-                       void *__ioaddr = ioaddr;                        \
+                       void __iomem *__ioaddr = ioaddr;                \
                        if ((unsigned long)__ptr & 2) {                 \
                                /*                                      \
                                 * We want 32bit alignment here.        \