Merge branch 'core-rcu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[pandora-kernel.git] / drivers / net / sky2.h

diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 318c9ae..0af31b8 100644 (file)
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -412,7 +412,7 @@ enum {
        Y2_IS_HW_ERR    = 1<<31,        /* Interrupt HW Error */
        Y2_IS_STAT_BMU  = 1<<30,        /* Status BMU Interrupt */
        Y2_IS_ASF       = 1<<29,        /* ASF subsystem Interrupt */
-
+       Y2_IS_CPU_TO    = 1<<28,        /* CPU Timeout */
        Y2_IS_POLL_CHK  = 1<<27,        /* Check IRQ from polling unit */
        Y2_IS_TWSI_RDY  = 1<<26,        /* IRQ on end of TWSI Tx */
        Y2_IS_IRQ_SW    = 1<<25,        /* SW forced IRQ        */
@@ -547,6 +547,8 @@ enum {
        CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
        CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
        CHIP_ID_YUKON_OPT  = 0xbc, /* YUKON-2 Optima */
+       CHIP_ID_YUKON_PRM  = 0xbd, /* YUKON-2 Optima Prime */
+       CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */
 };
 
 enum yukon_xl_rev {
@@ -1420,8 +1422,10 @@ enum {
        PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
        PHY_M_EC_DTE_D_ENA  = 1<<2, /* DTE Detect Enable (88E1111 only) */
        PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
-       PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};
+       PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */
 
+       PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */
+};
 #define PHY_M_EC_M_DSC(x)      ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
                                        /* 00=1x; 01=2x; 10=3x; 11=4x */
 #define PHY_M_EC_S_DSC(x)      ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
@@ -1807,10 +1811,11 @@ enum {
 };
 
 #define DATA_BLIND_VAL(x)      (((x)<<11) & GM_SMOD_DATABL_MSK)
-#define DATA_BLIND_DEF         0x04
-
 #define IPG_DATA_VAL(x)                (x & GM_SMOD_IPG_MSK)
-#define IPG_DATA_DEF           0x1e
+
+#define DATA_BLIND_DEF         0x04
+#define IPG_DATA_DEF_1000      0x1e
+#define IPG_DATA_DEF_10_100    0x18
 
 /*     GM_SMI_CTRL                     16 bit r/w      SMI Control Register */
 enum {
@@ -2281,6 +2286,7 @@ struct sky2_hw {
 #define SKY2_HW_ADV_POWER_CTL  0x00000080      /* additional PHY power regs */
 #define SKY2_HW_RSS_BROKEN     0x00000100
 #define SKY2_HW_VLAN_BROKEN     0x00000200
+#define SKY2_HW_RSS_CHKSUM     0x00000400      /* RSS requires chksum */
 
        u8                   chip_id;
        u8                   chip_rev;