/*******************************************************************************
Intel PRO/10GbE Linux driver
- Copyright(c) 1999 - 2006 Intel Corporation.
+ Copyright(c) 1999 - 2008 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
/* Local function prototypes */
-static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t * mc_addr);
+static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
-static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value);
+static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
static void ixgb_get_bus_info(struct ixgb_hw *hw);
-static boolean_t ixgb_link_reset(struct ixgb_hw *hw);
+static bool ixgb_link_reset(struct ixgb_hw *hw);
static void ixgb_optics_reset(struct ixgb_hw *hw);
static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
-static uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw,
- uint32_t reg_address,
- uint32_t phy_address,
- uint32_t device_type);
+static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
+ u32 reg_address,
+ u32 phy_address,
+ u32 device_type);
-static boolean_t ixgb_setup_fc(struct ixgb_hw *hw);
+static bool ixgb_setup_fc(struct ixgb_hw *hw);
-static boolean_t mac_addr_valid(uint8_t *mac_addr);
+static bool mac_addr_valid(u8 *mac_addr);
-static uint32_t ixgb_mac_reset(struct ixgb_hw *hw)
+static u32 ixgb_mac_reset(struct ixgb_hw *hw)
{
- uint32_t ctrl_reg;
+ u32 ctrl_reg;
ctrl_reg = IXGB_CTRL0_RST |
IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
-boolean_t
+bool
ixgb_adapter_stop(struct ixgb_hw *hw)
{
- uint32_t ctrl_reg;
- uint32_t icr_reg;
+ u32 ctrl_reg;
+ u32 icr_reg;
DEBUGFUNC("ixgb_adapter_stop");
/* If we are stopped or resetting exit gracefully and wait to be
* started again before accessing the hardware.
*/
- if(hw->adapter_stopped) {
+ if (hw->adapter_stopped) {
DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
- return FALSE;
+ return false;
}
/* Set the Adapter Stopped flag so other driver functions stop
* touching the Hardware.
*/
- hw->adapter_stopped = TRUE;
+ hw->adapter_stopped = true;
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
static ixgb_xpak_vendor
ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
{
- uint32_t i;
- uint16_t vendor_name[5];
+ u32 i;
+ u16 vendor_name[5];
ixgb_xpak_vendor xpak_vendor;
DEBUGFUNC("ixgb_identify_xpak_vendor");
* Leaves the transmit and receive units disabled and uninitialized.
*
* Returns:
- * TRUE if successful,
- * FALSE if unrecoverable problems were encountered.
+ * true if successful,
+ * false if unrecoverable problems were encountered.
*****************************************************************************/
-boolean_t
+bool
ixgb_init_hw(struct ixgb_hw *hw)
{
- uint32_t i;
- uint32_t ctrl_reg;
- boolean_t status;
+ u32 i;
+ u32 ctrl_reg;
+ bool status;
DEBUGFUNC("ixgb_init_hw");
/* Delay a few ms just to allow the reset to complete */
msleep(IXGB_DELAY_AFTER_EE_RESET);
- if (ixgb_get_eeprom_data(hw) == FALSE) {
- return(FALSE);
- }
+ if (!ixgb_get_eeprom_data(hw))
+ return false;
/* Use the device id to determine the type of phy/transceiver. */
hw->device_id = ixgb_get_ee_device_id(hw);
*/
if (!mac_addr_valid(hw->curr_mac_addr)) {
DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
- return(FALSE);
+ return(false);
}
/* tell the routines in this file they can access hardware again */
- hw->adapter_stopped = FALSE;
+ hw->adapter_stopped = false;
/* Fill in the bus_info structure */
ixgb_get_bus_info(hw);
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
- for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
/* Zero out the VLAN Filter Table Array */
* hw - Struct containing variables accessed by shared code
*
* Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
+ * of the receive address registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
*****************************************************************************/
static void
ixgb_init_rx_addrs(struct ixgb_hw *hw)
{
- uint32_t i;
+ u32 i;
DEBUGFUNC("ixgb_init_rx_addrs");
/* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
- for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
+ for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
/* Write high reg first to disable the AV bit first */
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
*****************************************************************************/
void
ixgb_mc_addr_list_update(struct ixgb_hw *hw,
- uint8_t *mc_addr_list,
- uint32_t mc_addr_count,
- uint32_t pad)
+ u8 *mc_addr_list,
+ u32 mc_addr_count,
+ u32 pad)
{
- uint32_t hash_value;
- uint32_t i;
- uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */
+ u32 hash_value;
+ u32 i;
+ u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
DEBUGFUNC("ixgb_mc_addr_list_update");
/* Clear RAR[1-15] */
DEBUGOUT(" Clearing RAR[1-15]\n");
- for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
+ for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
}
/* Clear the MTA */
DEBUGOUT(" Clearing MTA\n");
- for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
- }
/* Add the new addresses */
- for(i = 0; i < mc_addr_count; i++) {
+ for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
/* Place this multicast address in the RAR if there is room, *
* else put it in the MTA
*/
- if(rar_used_count < IXGB_RAR_ENTRIES) {
+ if (rar_used_count < IXGB_RAR_ENTRIES) {
ixgb_rar_set(hw,
mc_addr_list +
(i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)),
* Returns:
* The hash value
*****************************************************************************/
-static uint32_t
+static u32
ixgb_hash_mc_addr(struct ixgb_hw *hw,
- uint8_t *mc_addr)
+ u8 *mc_addr)
{
- uint32_t hash_value = 0;
+ u32 hash_value = 0;
DEBUGFUNC("ixgb_hash_mc_addr");
case 0:
/* [47:36] i.e. 0x563 for above example address */
hash_value =
- ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
+ ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
break;
case 1: /* [46:35] i.e. 0xAC6 for above example address */
hash_value =
- ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
+ ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
break;
case 2: /* [45:34] i.e. 0x5D8 for above example address */
hash_value =
- ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
+ ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
break;
case 3: /* [43:32] i.e. 0x634 for above example address */
- hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
+ hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
break;
default:
/* Invalid mc_filter_type, what should we do? */
*****************************************************************************/
static void
ixgb_mta_set(struct ixgb_hw *hw,
- uint32_t hash_value)
+ u32 hash_value)
{
- uint32_t hash_bit, hash_reg;
- uint32_t mta_reg;
+ u32 hash_bit, hash_reg;
+ u32 mta_reg;
/* The MTA is a register array of 128 32-bit registers.
* It is treated like an array of 4096 bits. We want to set
*****************************************************************************/
void
ixgb_rar_set(struct ixgb_hw *hw,
- uint8_t *addr,
- uint32_t index)
+ u8 *addr,
+ u32 index)
{
- uint32_t rar_low, rar_high;
+ u32 rar_low, rar_high;
DEBUGFUNC("ixgb_rar_set");
/* HW expects these in little endian so we reverse the byte order
* from network order (big endian) to little endian
*/
- rar_low = ((uint32_t) addr[0] |
- ((uint32_t)addr[1] << 8) |
- ((uint32_t)addr[2] << 16) |
- ((uint32_t)addr[3] << 24));
+ rar_low = ((u32) addr[0] |
+ ((u32)addr[1] << 8) |
+ ((u32)addr[2] << 16) |
+ ((u32)addr[3] << 24));
- rar_high = ((uint32_t) addr[4] |
- ((uint32_t)addr[5] << 8) |
+ rar_high = ((u32) addr[4] |
+ ((u32)addr[5] << 8) |
IXGB_RAH_AV);
IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
*****************************************************************************/
void
ixgb_write_vfta(struct ixgb_hw *hw,
- uint32_t offset,
- uint32_t value)
+ u32 offset,
+ u32 value)
{
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
return;
static void
ixgb_clear_vfta(struct ixgb_hw *hw)
{
- uint32_t offset;
+ u32 offset;
- for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
+ for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
return;
}
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
-static boolean_t
+static bool
ixgb_setup_fc(struct ixgb_hw *hw)
{
- uint32_t ctrl_reg;
- uint32_t pap_reg = 0; /* by default, assume no pause time */
- boolean_t status = TRUE;
+ u32 ctrl_reg;
+ u32 pap_reg = 0; /* by default, assume no pause time */
+ bool status = true;
DEBUGFUNC("ixgb_setup_fc");
/* Write the new settings */
IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
- if (pap_reg != 0) {
+ if (pap_reg != 0)
IXGB_WRITE_REG(hw, PAP, pap_reg);
- }
/* Set the flow control receive threshold registers. Normally,
* these registers will be set to a default threshold that may be
* ability to transmit pause frames in not enabled, then these
* registers will be set to 0.
*/
- if(!(hw->fc.type & ixgb_fc_tx_pause)) {
+ if (!(hw->fc.type & ixgb_fc_tx_pause)) {
IXGB_WRITE_REG(hw, FCRTL, 0);
IXGB_WRITE_REG(hw, FCRTH, 0);
} else {
/* We need to set up the Receive Threshold high and low water
* marks as well as (optionally) enabling the transmission of XON
* frames. */
- if(hw->fc.send_xon) {
+ if (hw->fc.send_xon) {
IXGB_WRITE_REG(hw, FCRTL,
(hw->fc.low_water | IXGB_FCRTL_XONE));
} else {
* This requires that first an address cycle command is sent, followed by a
* read command.
*****************************************************************************/
-static uint16_t
+static u16
ixgb_read_phy_reg(struct ixgb_hw *hw,
- uint32_t reg_address,
- uint32_t phy_address,
- uint32_t device_type)
+ u32 reg_address,
+ u32 phy_address,
+ u32 device_type)
{
- uint32_t i;
- uint32_t data;
- uint32_t command = 0;
+ u32 i;
+ u32 data;
+ u32 command = 0;
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
*/
data = IXGB_READ_REG(hw, MSRWD);
data >>= IXGB_MSRWD_READ_DATA_SHIFT;
- return((uint16_t) data);
+ return((u16) data);
}
/******************************************************************************
*****************************************************************************/
static void
ixgb_write_phy_reg(struct ixgb_hw *hw,
- uint32_t reg_address,
- uint32_t phy_address,
- uint32_t device_type,
- uint16_t data)
+ u32 reg_address,
+ u32 phy_address,
+ u32 device_type,
+ u16 data)
{
- uint32_t i;
- uint32_t command = 0;
+ u32 i;
+ u32 command = 0;
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
/* Put the data in the MDIO Read/Write Data register */
- IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data);
+ IXGB_WRITE_REG(hw, MSRWD, (u32)data);
/* Setup and write the address cycle command */
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
** from the CPU Write to the Ready bit assertion.
**************************************************************/
- for(i = 0; i < 10; i++)
+ for (i = 0; i < 10; i++)
{
udelay(10);
void
ixgb_check_for_link(struct ixgb_hw *hw)
{
- uint32_t status_reg;
- uint32_t xpcss_reg;
+ u32 status_reg;
+ u32 xpcss_reg;
DEBUGFUNC("ixgb_check_for_link");
if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
(status_reg & IXGB_STATUS_LU)) {
- hw->link_up = TRUE;
+ hw->link_up = true;
} else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
(status_reg & IXGB_STATUS_LU)) {
DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
}
/******************************************************************************
- * Check for a bad link condition that may have occured.
+ * Check for a bad link condition that may have occurred.
* The indication is that the RFC / LFC registers may be incrementing
* continually. A full adapter reset is required to recover.
*
*
* Called by any function that needs to check the link status of the adapter.
*****************************************************************************/
-boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw)
+bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
{
- uint32_t newLFC, newRFC;
- boolean_t bad_link_returncode = FALSE;
+ u32 newLFC, newRFC;
+ bool bad_link_returncode = false;
if (hw->phy_type == ixgb_phy_type_txn17401) {
newLFC = IXGB_READ_REG(hw, LFC);
|| (hw->lastRFC + 250 < newRFC)) {
DEBUGOUT
("BAD LINK! too many LFC/RFC since last check\n");
- bad_link_returncode = TRUE;
+ bad_link_returncode = true;
}
hw->lastLFC = newLFC;
hw->lastRFC = newRFC;
static void
ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
{
- volatile uint32_t temp_reg;
+ volatile u32 temp_reg;
DEBUGFUNC("ixgb_clear_hw_cntrs");
/* if we are stopped or resetting exit gracefully */
- if(hw->adapter_stopped) {
+ if (hw->adapter_stopped) {
DEBUGOUT("Exiting because the adapter is stopped!!!\n");
return;
}
void
ixgb_led_on(struct ixgb_hw *hw)
{
- uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
+ u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
/* To turn on the LED, clear software-definable pin 0 (SDP0). */
ctrl0_reg &= ~IXGB_CTRL0_SDP0;
void
ixgb_led_off(struct ixgb_hw *hw)
{
- uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
+ u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
/* To turn off the LED, set software-definable pin 0 (SDP0). */
ctrl0_reg |= IXGB_CTRL0_SDP0;
static void
ixgb_get_bus_info(struct ixgb_hw *hw)
{
- uint32_t status_reg;
+ u32 status_reg;
status_reg = IXGB_READ_REG(hw, STATUS);
* mac_addr - pointer to MAC address.
*
*****************************************************************************/
-static boolean_t
-mac_addr_valid(uint8_t *mac_addr)
+static bool
+mac_addr_valid(u8 *mac_addr)
{
- boolean_t is_valid = TRUE;
+ bool is_valid = true;
DEBUGFUNC("mac_addr_valid");
/* Make sure it is not a multicast address */
if (IS_MULTICAST(mac_addr)) {
DEBUGOUT("MAC address is multicast\n");
- is_valid = FALSE;
+ is_valid = false;
}
/* Not a broadcast address */
else if (IS_BROADCAST(mac_addr)) {
DEBUGOUT("MAC address is broadcast\n");
- is_valid = FALSE;
+ is_valid = false;
}
/* Reject the zero address */
else if (mac_addr[0] == 0 &&
mac_addr[4] == 0 &&
mac_addr[5] == 0) {
DEBUGOUT("MAC address is all zeros\n");
- is_valid = FALSE;
+ is_valid = false;
}
return (is_valid);
}
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
-static boolean_t
+static bool
ixgb_link_reset(struct ixgb_hw *hw)
{
- boolean_t link_status = FALSE;
- uint8_t wait_retries = MAX_RESET_ITERATIONS;
- uint8_t lrst_retries = MAX_RESET_ITERATIONS;
+ bool link_status = false;
+ u8 wait_retries = MAX_RESET_ITERATIONS;
+ u8 lrst_retries = MAX_RESET_ITERATIONS;
do {
/* Reset the link */
link_status =
((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
&& (IXGB_READ_REG(hw, XPCSS) &
- IXGB_XPCSS_ALIGN_STATUS)) ? TRUE : FALSE;
+ IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
} while (!link_status && --wait_retries);
} while (!link_status && --lrst_retries);
ixgb_optics_reset(struct ixgb_hw *hw)
{
if (hw->phy_type == ixgb_phy_type_txn17401) {
- uint16_t mdio_reg;
+ u16 mdio_reg;
ixgb_write_phy_reg(hw,
MDIO_PMA_PMD_CR1,
git.openpandora.org / pandora-kernel.git / blobdiff