#include <linux/mtd/nand_ecc.h>
static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-nand_info_t nand_info[1];
+static struct mtd_info *mtd;
static struct nand_chip nand_chip;
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
static int nand_command(int block, int page, uint32_t offs,
u8 cmd)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this->cmd_ctrl;
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
/* Emulate NAND_CMD_READOOB */
}
/* Begin command latch cycle */
- hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_RESET) {
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!this->dev_ready(&nand_info[0]))
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!this->dev_ready(mtd))
;
return 0;
}
/* Set ALE and clear CLE to start address cycle */
/* Column address */
- hwctrl(&nand_info[0], offs & 0xff,
+ hwctrl(mtd, offs & 0xff,
NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+ hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
/* Row address */
- hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+ if (cmd != NAND_CMD_RNDOUT) {
+ hwctrl(mtd, (page_addr & 0xff),
+ NAND_CTRL_ALE); /* A[19:12] */
+ hwctrl(mtd, ((page_addr >> 8) & 0xff),
NAND_CTRL_ALE); /* A[27:20] */
#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices > 128MiB */
- hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+ /* One more address cycle for devices > 128MiB */
+ hwctrl(mtd, (page_addr >> 16) & 0x0f,
NAND_CTRL_ALE); /* A[31:28] */
#endif
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ }
+
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
/* Latch in address */
- hwctrl(&nand_info[0], NAND_CMD_READSTART,
+ hwctrl(mtd, NAND_CMD_READSTART,
NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/*
* Wait a while for the data to be ready
*/
- while (!this->dev_ready(&nand_info[0]))
+ while (!this->dev_ready(mtd))
;
} else if (cmd == NAND_CMD_RNDOUT) {
- hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+ hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
NAND_CTRL_CHANGE);
- hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
}
return 0;
static int nand_is_bad_block(int block)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
NAND_CMD_READOOB);
static int nand_read_page(int block, int page, void *dst)
{
- struct nand_chip *this = nand_info[0].priv;
+ struct nand_chip *this = mtd->priv;
u_char ecc_calc[ECCTOTAL];
u_char ecc_code[ECCTOTAL];
u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
nand_command(block, page, 0, NAND_CMD_READ0);
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
+ this->ecc.hwctl(mtd, NAND_ECC_READ);
nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], p, eccsize);
+ this->read_buf(mtd, p, eccsize);
nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
- this->read_buf(&nand_info[0], oob, eccbytes);
- this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
+ this->read_buf(mtd, oob, eccbytes);
+ this->ecc.calculate(mtd, p, &ecc_calc[i]);
data_pos += eccsize;
oob_pos += eccbytes;
* from correct_data(). We just hope that all possible errors
* are corrected by this routine.
*/
- this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
+ this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
}
return 0;
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
{
unsigned int block, lastblock;
- unsigned int page;
+ unsigned int page, page_offset;
/*
* offs has to be aligned to a page address!
block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+ page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
while (block <= lastblock) {
if (!nand_is_bad_block(block)) {
*/
while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
nand_read_page(block, page, dst);
+ /*
+ * When offs is not aligned to page address the
+ * extra offset is copied to dst as well. Copy
+ * the image such that its first byte will be
+ * at the dst.
+ */
+ if (unlikely(page_offset)) {
+ memmove(dst, dst + page_offset,
+ CONFIG_SYS_NAND_PAGE_SIZE);
+ dst = (void *)((int)dst - page_offset);
+ page_offset = 0;
+ }
dst += CONFIG_SYS_NAND_PAGE_SIZE;
page++;
}
/*
* Init board specific nand support
*/
- nand_info[0].priv = &nand_chip;
+ mtd = &nand_chip.mtd;
nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
(void __iomem *)CONFIG_SYS_NAND_BASE;
board_nand_init(&nand_chip);
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], 0);
+ nand_chip.select_chip(mtd, 0);
/* NAND chip may require reset after power-on */
nand_command(0, 0, 0, NAND_CMD_RESET);
void nand_deselect(void)
{
if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info[0], -1);
+ nand_chip.select_chip(mtd, -1);
}
git.openpandora.org / pandora-u-boot.git / blobdiff