/* S2 DEMOD */
#define STB0899_OFF0_DMD_STATUS 0xf300
#define STB0899_BASE_DMD_STATUS 0x00000000
-#define STB0899_IF_AGC_LOCK (0x01 << 0)
+#define STB0899_IF_AGC_LOCK (0x01 << 8)
#define STB0899_OFFST_IF_AGC_LOCK 0
#define STB0899_WIDTH_IF_AGC_LOCK 1
#define STB0899_OFF0_CRL_FREQ 0xf304
#define STB0899_BASE_CRL_FREQ 0x00000000
-#define STB0899_CARR_FREQ (0x1fffffff << 0)
+#define STB0899_CARR_FREQ (0x3fffffff << 0)
#define STB0899_OFFST_CARR_FREQ 0
#define STB0899_WIDTH_CARR_FREQ 30
#define STB0899_OFFST_CSM_GAMMA_ACQ 0
#define STB0899_WIDTH_CSM_GAMMA_ACQ 9
-#define STB0899_OFF0_CSM_CNTRL3 0xf320
+#define STB0899_OFF0_CSM_CNTRL3 0xf318
#define STB0899_BASE_CSM_CNTRL3 0x00000400
#define STB0899_CSM_GAMMA_RHO_TRACK (0x1ff << 9)
#define STB0899_OFFST_CSM_GAMMA_RHOTRACK 9
#define STB0899_OFFST_CSM_GAMMA_TRACK 0
#define STB0899_WIDTH_CSM_GAMMA_TRACK 9
-#define STB0899_OFF0_CSM_CNTRL4 0xf324
+#define STB0899_OFF0_CSM_CNTRL4 0xf31c
#define STB0899_BASE_CSM_CNTRL4 0x00000400
#define STB0899_CSM_PHASEDIFF_THRESH (0x0f << 8)
#define STB0899_OFFST_CSM_PHASEDIFF_THRESH 8
/* General Purpose */
#define STB0899_SYSREG 0xf101
#define STB0899_ACRPRESC 0xf110
+#define STB0899_OFFST_RSVD2 7
+#define STB0899_WIDTH_RSVD2 1
+#define STB0899_OFFST_ACRPRESC 4
+#define STB0899_WIDTH_ACRPRESC 3
+#define STB0899_OFFST_RSVD1 3
+#define STB0899_WIDTH_RSVD1 1
+#define STB0899_OFFST_ACRPRESC2 0
+#define STB0899_WIDTH_ACRPRESC2 3
+
#define STB0899_ACRDIV1 0xf111
#define STB0899_ACRDIV2 0xf112
#define STB0899_DACR1 0xf113