};
static const char *pm_state_types[5] = {
- "Default",
+ "",
"Powersave",
"Battery",
"Balanced",
pm_state_types[rdev->pm.power_state[i].type],
is_default ? "(default)" : "");
if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
- DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
+ DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
DRM_INFO("\tSingle display only\n");
DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
- if (radeon_dynpm != -1 && radeon_dynpm) {
+ if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
rdev->pm.state = PM_STATE_PAUSED;
DRM_INFO("radeon: dynamic power management enabled\n");
}
void radeon_pm_fini(struct radeon_device *rdev)
{
+ if (rdev->pm.state != PM_STATE_DISABLED) {
+ /* cancel work */
+ cancel_delayed_work_sync(&rdev->pm.idle_work);
+ /* reset default clocks */
+ rdev->pm.state = PM_STATE_DISABLED;
+ rdev->pm.planned_action = PM_ACTION_DEFAULT;
+ radeon_pm_set_clocks(rdev);
+ }
+
if (rdev->pm.i2c_bus)
radeon_i2c_destroy(rdev->pm.i2c_bus);
}
}
}
+ /* update display watermarks based on new power state */
+ radeon_update_bandwidth_info(rdev);
+ if (rdev->pm.active_crtc_count)
+ radeon_bandwidth_update(rdev);
+
mutex_unlock(&rdev->cp.mutex);
}