/*
* Clear GPU surface registers.
*/
-static void radeon_surface_init(struct radeon_device *rdev)
+void radeon_surface_init(struct radeon_device *rdev)
{
/* FIXME: check this out */
if (rdev->family < CHIP_R600) {
i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
0);
}
+ /* enable surfaces */
+ WREG32(RADEON_SURFACE_CNTL, 0);
}
}
/*
* GPU scratch registers helpers function.
*/
-static void radeon_scratch_init(struct radeon_device *rdev)
+void radeon_scratch_init(struct radeon_device *rdev)
{
int i;
if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
/* vram location was already setup try to put gtt after
* if it fits */
- tmp = rdev->mc.vram_location + rdev->mc.vram_size;
+ tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
rdev->mc.gtt_location = tmp;
} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
/* gtt location was already setup try to put vram before
* if it fits */
- if (rdev->mc.vram_size < rdev->mc.gtt_location) {
+ if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
rdev->mc.vram_location = 0;
} else {
tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
- tmp += (rdev->mc.vram_size - 1);
- tmp &= ~(rdev->mc.vram_size - 1);
- if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
+ tmp += (rdev->mc.mc_vram_size - 1);
+ tmp &= ~(rdev->mc.mc_vram_size - 1);
+ if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
rdev->mc.vram_location = tmp;
} else {
printk(KERN_ERR "[drm] vram too big to fit "
}
} else {
rdev->mc.vram_location = 0;
- rdev->mc.gtt_location = rdev->mc.vram_size;
+ tmp = rdev->mc.mc_vram_size;
+ tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
+ rdev->mc.gtt_location = tmp;
}
- DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
+ DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
- rdev->mc.vram_location,
- rdev->mc.vram_location + rdev->mc.vram_size - 1);
- DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
+ (unsigned)rdev->mc.vram_location,
+ (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
+ DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
- rdev->mc.gtt_location,
- rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
+ (unsigned)rdev->mc.gtt_location,
+ (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
return 0;
}
}
+int radeon_dummy_page_init(struct radeon_device *rdev)
+{
+ rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
+ if (rdev->dummy_page.page == NULL)
+ return -ENOMEM;
+ rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
+ 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ if (!rdev->dummy_page.addr) {
+ __free_page(rdev->dummy_page.page);
+ rdev->dummy_page.page = NULL;
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+void radeon_dummy_page_fini(struct radeon_device *rdev)
+{
+ if (rdev->dummy_page.page == NULL)
+ return;
+ pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
+ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+ __free_page(rdev->dummy_page.page);
+ rdev->dummy_page.page = NULL;
+}
+
/*
* Registers accessors functions.
void radeon_register_accessor_init(struct radeon_device *rdev)
{
- rdev->mm_rreg = &r100_mm_rreg;
- rdev->mm_wreg = &r100_mm_wreg;
rdev->mc_rreg = &radeon_invalid_rreg;
rdev->mc_wreg = &radeon_invalid_wreg;
rdev->pll_rreg = &radeon_invalid_rreg;
rdev->pll_wreg = &radeon_invalid_wreg;
- rdev->pcie_rreg = &radeon_invalid_rreg;
- rdev->pcie_wreg = &radeon_invalid_wreg;
rdev->pciep_rreg = &radeon_invalid_rreg;
rdev->pciep_wreg = &radeon_invalid_wreg;
/* Don't change order as we are overridding accessor. */
if (rdev->family < CHIP_RV515) {
- rdev->pcie_rreg = &rv370_pcie_rreg;
- rdev->pcie_wreg = &rv370_pcie_wreg;
- }
- if (rdev->family >= CHIP_RV515) {
- rdev->pcie_rreg = &rv515_pcie_rreg;
- rdev->pcie_wreg = &rv515_pcie_wreg;
+ rdev->pcie_reg_mask = 0xff;
+ } else {
+ rdev->pcie_reg_mask = 0x7ff;
}
/* FIXME: not sure here */
if (rdev->family <= CHIP_R580) {
rdev->pll_rreg = &r100_pll_rreg;
rdev->pll_wreg = &r100_pll_wreg;
}
+ if (rdev->family >= CHIP_R420) {
+ rdev->mc_rreg = &r420_mc_rreg;
+ rdev->mc_wreg = &r420_mc_wreg;
+ }
if (rdev->family >= CHIP_RV515) {
rdev->mc_rreg = &rv515_mc_rreg;
rdev->mc_wreg = &rv515_mc_wreg;
case CHIP_RV635:
case CHIP_RV670:
case CHIP_RS780:
+ case CHIP_RS880:
+ rdev->asic = &r600_asic;
+ break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
+ case CHIP_RV740:
+ rdev->asic = &rv770_asic;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
struct pci_dev *pdev,
uint32_t flags)
{
- int r, ret;
+ int r, ret = 0;
+ int dma_bits;
DRM_INFO("radeon: Initializing kernel modesetting.\n");
rdev->shutdown = false;
if (r) {
return r;
}
- r = radeon_init(rdev);
- if (r) {
- return r;
- }
- /* Report DMA addressing limitation */
- r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
+ /* set DMA mask + need_dma32 flags.
+ * PCIE - can handle 40-bits.
+ * IGP - can handle 40-bits (in theory)
+ * AGP - generally dma32 is safest
+ * PCI - only dma32
+ */
+ rdev->need_dma32 = false;
+ if (rdev->flags & RADEON_IS_AGP)
+ rdev->need_dma32 = true;
+ if (rdev->flags & RADEON_IS_PCI)
+ rdev->need_dma32 = true;
+
+ dma_bits = rdev->need_dma32 ? 32 : 40;
+ r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
if (r) {
printk(KERN_WARNING "radeon: No suitable DMA available.\n");
}
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
- /* Setup errata flags */
- radeon_errata(rdev);
- /* Initialize scratch registers */
- radeon_scratch_init(rdev);
- /* Initialize surface registers */
- radeon_surface_init(rdev);
-
- /* TODO: disable VGA need to use VGA request */
- /* BIOS*/
- if (!radeon_get_bios(rdev)) {
- if (ASIC_IS_AVIVO(rdev))
- return -EINVAL;
- }
- if (rdev->is_atom_bios) {
- r = radeon_atombios_init(rdev);
+ rdev->new_init_path = false;
+ r = radeon_init(rdev);
+ if (r) {
+ return r;
+ }
+ if (!rdev->new_init_path) {
+ /* Setup errata flags */
+ radeon_errata(rdev);
+ /* Initialize scratch registers */
+ radeon_scratch_init(rdev);
+ /* Initialize surface registers */
+ radeon_surface_init(rdev);
+
+ /* TODO: disable VGA need to use VGA request */
+ /* BIOS*/
+ if (!radeon_get_bios(rdev)) {
+ if (ASIC_IS_AVIVO(rdev))
+ return -EINVAL;
+ }
+ if (rdev->is_atom_bios) {
+ r = radeon_atombios_init(rdev);
+ if (r) {
+ return r;
+ }
+ } else {
+ r = radeon_combios_init(rdev);
+ if (r) {
+ return r;
+ }
+ }
+ /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+ if (radeon_gpu_reset(rdev)) {
+ /* FIXME: what do we want to do here ? */
+ }
+ /* check if cards are posted or not */
+ if (!radeon_card_posted(rdev) && rdev->bios) {
+ DRM_INFO("GPU not posted. posting now...\n");
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ }
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
if (r) {
return r;
}
- } else {
- r = radeon_combios_init(rdev);
+ /* Get vram informations */
+ radeon_vram_info(rdev);
+
+ /* Add an MTRR for the VRAM */
+ rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
+ MTRR_TYPE_WRCOMB, 1);
+ DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
+ (unsigned)(rdev->mc.mc_vram_size >> 20),
+ (unsigned)(rdev->mc.aper_size >> 20));
+ DRM_INFO("RAM width %dbits %cDR\n",
+ rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
+ /* Initialize memory controller (also test AGP) */
+ r = radeon_mc_init(rdev);
if (r) {
return r;
}
- }
- /* Reset gpu before posting otherwise ATOM will enter infinite loop */
- if (radeon_gpu_reset(rdev)) {
- /* FIXME: what do we want to do here ? */
- }
- /* check if cards are posted or not */
- if (!radeon_card_posted(rdev) && rdev->bios) {
- DRM_INFO("GPU not posted. posting now...\n");
- if (rdev->is_atom_bios) {
- atom_asic_init(rdev->mode_info.atom_context);
- } else {
- radeon_combios_asic_init(rdev->ddev);
- }
- }
- /* Get vram informations */
- radeon_vram_info(rdev);
- /* Device is severly broken if aper size > vram size.
- * for RN50/M6/M7 - Novell bug 204882 ?
- */
- if (rdev->mc.vram_size < rdev->mc.aper_size) {
- rdev->mc.aper_size = rdev->mc.vram_size;
- }
- /* Add an MTRR for the VRAM */
- rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
- MTRR_TYPE_WRCOMB, 1);
- DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
- rdev->mc.vram_size >> 20,
- (unsigned)rdev->mc.aper_size >> 20);
- DRM_INFO("RAM width %dbits %cDR\n",
- rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
- /* Initialize clocks */
- r = radeon_clocks_init(rdev);
- if (r) {
- return r;
- }
- /* Initialize memory controller (also test AGP) */
- r = radeon_mc_init(rdev);
- if (r) {
- return r;
- }
- /* Fence driver */
- r = radeon_fence_driver_init(rdev);
- if (r) {
- return r;
- }
- r = radeon_irq_kms_init(rdev);
- if (r) {
- return r;
- }
- /* Memory manager */
- r = radeon_object_init(rdev);
- if (r) {
- return r;
- }
- /* Initialize GART (initialize after TTM so we can allocate
- * memory through TTM but finalize after TTM) */
- r = radeon_gart_enable(rdev);
- if (!r) {
- r = radeon_gem_init(rdev);
- }
-
- /* 1M ring buffer */
- if (!r) {
- r = radeon_cp_init(rdev, 1024 * 1024);
- }
- if (!r) {
- r = radeon_wb_init(rdev);
+ /* Fence driver */
+ r = radeon_fence_driver_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
return r;
}
- }
- if (!r) {
- r = radeon_ib_pool_init(rdev);
+ r = radeon_irq_kms_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
return r;
}
- }
- if (!r) {
- r = radeon_ib_test(rdev);
+ /* Memory manager */
+ r = radeon_object_init(rdev);
if (r) {
- DRM_ERROR("radeon: failled testing IB (%d).\n", r);
return r;
}
+ /* Initialize GART (initialize after TTM so we can allocate
+ * memory through TTM but finalize after TTM) */
+ r = radeon_gart_enable(rdev);
+ if (!r) {
+ r = radeon_gem_init(rdev);
+ }
+
+ /* 1M ring buffer */
+ if (!r) {
+ r = radeon_cp_init(rdev, 1024 * 1024);
+ }
+ if (!r) {
+ r = radeon_wb_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
+ return r;
+ }
+ }
+ if (!r) {
+ r = radeon_ib_pool_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+ return r;
+ }
+ }
+ if (!r) {
+ r = radeon_ib_test(rdev);
+ if (r) {
+ DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+ return r;
+ }
+ }
+ ret = r;
}
- ret = r;
r = radeon_modeset_init(rdev);
if (r) {
return r;
if (!ret) {
DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
}
+ if (radeon_testing) {
+ radeon_test_moves(rdev);
+ }
if (radeon_benchmarking) {
radeon_benchmark(rdev);
}
rdev->shutdown = true;
/* Order matter so becarefull if you rearrange anythings */
radeon_modeset_fini(rdev);
- radeon_ib_pool_fini(rdev);
- radeon_cp_fini(rdev);
- radeon_wb_fini(rdev);
- radeon_gem_fini(rdev);
- radeon_object_fini(rdev);
- /* mc_fini must be after object_fini */
- radeon_mc_fini(rdev);
+ if (!rdev->new_init_path) {
+ radeon_ib_pool_fini(rdev);
+ radeon_cp_fini(rdev);
+ radeon_wb_fini(rdev);
+ radeon_gem_fini(rdev);
+ radeon_mc_fini(rdev);
#if __OS_HAS_AGP
- radeon_agp_fini(rdev);
+ radeon_agp_fini(rdev);
#endif
- radeon_irq_kms_fini(rdev);
- radeon_fence_driver_fini(rdev);
- radeon_clocks_fini(rdev);
- if (rdev->is_atom_bios) {
- radeon_atombios_fini(rdev);
+ radeon_irq_kms_fini(rdev);
+ radeon_fence_driver_fini(rdev);
+ radeon_clocks_fini(rdev);
+ radeon_object_fini(rdev);
+ if (rdev->is_atom_bios) {
+ radeon_atombios_fini(rdev);
+ } else {
+ radeon_combios_fini(rdev);
+ }
+ kfree(rdev->bios);
+ rdev->bios = NULL;
} else {
- radeon_combios_fini(rdev);
+ radeon_fini(rdev);
}
- kfree(rdev->bios);
- rdev->bios = NULL;
iounmap(rdev->rmmio);
rdev->rmmio = NULL;
}
/* wait for gpu to finish processing current batch */
radeon_fence_wait_last(rdev);
- radeon_cp_disable(rdev);
- radeon_gart_disable(rdev);
-
+ if (!rdev->new_init_path) {
+ radeon_cp_disable(rdev);
+ radeon_gart_disable(rdev);
+ } else {
+ radeon_suspend(rdev);
+ }
/* evict remaining vram memory */
radeon_object_evict_vram(rdev);
if (radeon_gpu_reset(rdev)) {
/* FIXME: what do we want to do here ? */
}
- /* post card */
- if (rdev->is_atom_bios) {
- atom_asic_init(rdev->mode_info.atom_context);
+ if (!rdev->new_init_path) {
+ /* post card */
+ if (rdev->is_atom_bios) {
+ atom_asic_init(rdev->mode_info.atom_context);
+ } else {
+ radeon_combios_asic_init(rdev->ddev);
+ }
+ /* Initialize clocks */
+ r = radeon_clocks_init(rdev);
+ if (r) {
+ release_console_sem();
+ return r;
+ }
+ /* Enable IRQ */
+ rdev->irq.sw_int = true;
+ radeon_irq_set(rdev);
+ /* Initialize GPU Memory Controller */
+ r = radeon_mc_init(rdev);
+ if (r) {
+ goto out;
+ }
+ r = radeon_gart_enable(rdev);
+ if (r) {
+ goto out;
+ }
+ r = radeon_cp_init(rdev, rdev->cp.ring_size);
+ if (r) {
+ goto out;
+ }
} else {
- radeon_combios_asic_init(rdev->ddev);
- }
- /* Initialize clocks */
- r = radeon_clocks_init(rdev);
- if (r) {
- release_console_sem();
- return r;
- }
- /* Enable IRQ */
- rdev->irq.sw_int = true;
- radeon_irq_set(rdev);
- /* Initialize GPU Memory Controller */
- r = radeon_mc_init(rdev);
- if (r) {
- goto out;
- }
- r = radeon_gart_enable(rdev);
- if (r) {
- goto out;
- }
- r = radeon_cp_init(rdev, rdev->cp.ring_size);
- if (r) {
- goto out;
+ radeon_resume(rdev);
}
out:
fb_set_suspend(rdev->fbdev_info, 0);