drm/radeon: Writeback endian fixes

[pandora-kernel.git] / drivers / gpu / drm / radeon / r600_cp.c

diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index c3ab959..45fd592 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -1802,8 +1802,8 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
        /* Set ring buffer size */
 #ifdef __BIG_ENDIAN
        RADEON_WRITE(R600_CP_RB_CNTL,
-                    RADEON_BUF_SWAP_32BIT |
-                    RADEON_RB_NO_UPDATE |
+                    R600_BUF_SWAP_32BIT |
+                    R600_RB_NO_UPDATE |
                     (dev_priv->ring.rptr_update_l2qw << 8) |
                     dev_priv->ring.size_l2qw);
 #else
@@ -1820,15 +1820,15 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
 
 #ifdef __BIG_ENDIAN
        RADEON_WRITE(R600_CP_RB_CNTL,
-                    RADEON_BUF_SWAP_32BIT |
-                    RADEON_RB_NO_UPDATE |
-                    RADEON_RB_RPTR_WR_ENA |
+                    R600_BUF_SWAP_32BIT |
+                    R600_RB_NO_UPDATE |
+                    R600_RB_RPTR_WR_ENA |
                     (dev_priv->ring.rptr_update_l2qw << 8) |
                     dev_priv->ring.size_l2qw);
 #else
        RADEON_WRITE(R600_CP_RB_CNTL,
-                    RADEON_RB_NO_UPDATE |
-                    RADEON_RB_RPTR_WR_ENA |
+                    R600_RB_NO_UPDATE |
+                    R600_RB_RPTR_WR_ENA |
                     (dev_priv->ring.rptr_update_l2qw << 8) |
                     dev_priv->ring.size_l2qw);
 #endif
@@ -1851,13 +1851,8 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
                        - ((unsigned long) dev->sg->virtual)
                        + dev_priv->gart_vm_start;
        }
-       RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
-#ifdef __BIG_ENDIAN
-                    (2 << 0) |
-#endif
-                    (rptr_addr & 0xfffffffc));
-       RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
-                    upper_32_bits(rptr_addr));
+       RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
+       RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
 
 #ifdef __BIG_ENDIAN
        RADEON_WRITE(R600_CP_RB_CNTL,