drm/radeon: Writeback endian fixes
[pandora-kernel.git] / drivers / gpu / drm / radeon / r600.c
index f79d2cc..1741af8 100644 (file)
@@ -1662,6 +1662,7 @@ void r600_gpu_init(struct radeon_device *rdev)
                                                                               R6XX_MAX_BACKENDS_MASK) >> 16)),
                                                        (cc_rb_backend_disable >> 16));
        rdev->config.r600.tile_config = tiling_config;
+       rdev->config.r600.backend_map = backend_map;
        tiling_config |= BACKEND_MAP(backend_map);
        WREG32(GB_TILING_CONFIG, tiling_config);
        WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
@@ -2212,9 +2213,6 @@ int r600_cp_resume(struct radeon_device *rdev)
 
        /* set the wb address whether it's enabled or not */
        WREG32(CP_RB_RPTR_ADDR,
-#ifdef __BIG_ENDIAN
-              RB_RPTR_SWAP(2) |
-#endif
               ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
        WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
@@ -2628,6 +2626,7 @@ void r600_fini(struct radeon_device *rdev)
        r600_cp_fini(rdev);
        r600_irq_fini(rdev);
        radeon_wb_fini(rdev);
+       radeon_ib_pool_fini(rdev);
        radeon_irq_kms_fini(rdev);
        r600_pcie_gart_fini(rdev);
        radeon_agp_fini(rdev);
@@ -2993,10 +2992,6 @@ int r600_irq_init(struct radeon_device *rdev)
        /* RPTR_REARM only works if msi's are enabled */
        if (rdev->msi_enabled)
                ih_cntl |= RPTR_REARM;
-
-#ifdef __BIG_ENDIAN
-       ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
-#endif
        WREG32(IH_CNTL, ih_cntl);
 
        /* force the active interrupt state to all disabled */