drm/i915: Disable AsyncFlip performance optimisations

[pandora-kernel.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 93819f8..38a7793 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -399,12 +399,20 @@ static int init_render_ring(struct intel_ring_buffer *ring)
        if (INTEL_INFO(dev)->gen > 3) {
                int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
                I915_WRITE(MI_MODE, mode);
-               if (IS_GEN7(dev))
-                       I915_WRITE(GFX_MODE_GEN7,
-                                  GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
-                                  GFX_MODE_ENABLE(GFX_REPLAY_MODE));
        }
 
+       /* We need to disable the AsyncFlip performance optimisations in order
+        * to use MI_WAIT_FOR_EVENT within the CS. It should already be
+        * programmed to '1' on all products.
+        */
+       if (INTEL_INFO(dev)->gen >= 6)
+               I915_WRITE(MI_MODE, GFX_MODE_ENABLE(ASYNC_FLIP_PERF_DISABLE));
+
+       if (IS_GEN7(dev))
+               I915_WRITE(GFX_MODE_GEN7,
+                          GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
+                          GFX_MODE_ENABLE(GFX_REPLAY_MODE));
+
        if (INTEL_INFO(dev)->gen >= 5) {
                ret = init_pipe_control(ring);
                if (ret)