Merge 'staging-next' to Linus's tree

[pandora-kernel.git] / drivers / gpio / timbgpio.c

diff --git a/drivers/gpio/timbgpio.c b/drivers/gpio/timbgpio.c
index ac4d0f0..4529366 100644 (file)
--- a/drivers/gpio/timbgpio.c
+++ b/drivers/gpio/timbgpio.c
@@ -47,6 +47,7 @@ struct timbgpio {
        spinlock_t              lock; /* mutual exclusion */
        struct gpio_chip        gpio;
        int                     irq_base;
+       unsigned long           last_ier;
 };
 
 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
@@ -112,16 +113,24 @@ static void timbgpio_irq_disable(unsigned irq)
 {
        struct timbgpio *tgpio = get_irq_chip_data(irq);
        int offset = irq - tgpio->irq_base;
+       unsigned long flags;
 
-       timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
+       spin_lock_irqsave(&tgpio->lock, flags);
+       tgpio->last_ier &= ~(1 << offset);
+       iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
+       spin_unlock_irqrestore(&tgpio->lock, flags);
 }
 
 static void timbgpio_irq_enable(unsigned irq)
 {
        struct timbgpio *tgpio = get_irq_chip_data(irq);
        int offset = irq - tgpio->irq_base;
+       unsigned long flags;
 
-       timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
+       spin_lock_irqsave(&tgpio->lock, flags);
+       tgpio->last_ier |= 1 << offset;
+       iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
+       spin_unlock_irqrestore(&tgpio->lock, flags);
 }
 
 static int timbgpio_irq_type(unsigned irq, unsigned trigger)
@@ -131,6 +140,7 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
        unsigned long flags;
        u32 lvr, flr, bflr = 0;
        u32 ver;
+       int ret = 0;
 
        if (offset < 0 || offset > tgpio->gpio.ngpio)
                return -EINVAL;
@@ -154,8 +164,10 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
        }
 
        if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
-               if (ver < 3)
-                       return -EINVAL;
+               if (ver < 3) {
+                       ret = -EINVAL;
+                       goto out;
+               }
                else {
                        flr |= 1 << offset;
                        bflr |= 1 << offset;
@@ -175,9 +187,10 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
                iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
 
        iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
-       spin_unlock_irqrestore(&tgpio->lock, flags);
 
-       return 0;
+out:
+       spin_unlock_irqrestore(&tgpio->lock, flags);
+       return ret;
 }
 
 static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
@@ -190,8 +203,16 @@ static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
        ipr = ioread32(tgpio->membase + TGPIO_IPR);
        iowrite32(ipr, tgpio->membase + TGPIO_ICR);
 
+       /*
+        * Some versions of the hardware trash the IER register if more than
+        * one interrupt is received simultaneously.
+        */
+       iowrite32(0, tgpio->membase + TGPIO_IER);
+
        for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
                generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
+
+       iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
 }
 
 static struct irq_chip timbgpio_irqchip = {