mci->edac_ctl_cap = EDAC_FLAG_SECDED;
mci->mod_name = DRV_NAME;
+#ifdef __tilegx__
+ mci->ctl_name = "TILEGx_Memory_Controller";
+#else
mci->ctl_name = "TILEPro_Memory_Controller";
+#endif
mci->dev_name = dev_name(&pdev->dev);
mci->edac_check = tile_edac_check;