amd64_edac: Fix DCT argument type

[pandora-kernel.git] / drivers / edac / amd64_edac.c

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 2425332..cc4f887 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -768,8 +768,7 @@ static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt)
        return edac_cap;
 }
 
-
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt);
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *, u8);
 
 static void amd64_dump_dramcfg_low(u32 dclr, int chan)
 {
@@ -817,13 +816,13 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
 
        debugf1("  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
 
-       amd64_debug_display_dimm_sizes(0, pvt);
+       amd64_debug_display_dimm_sizes(pvt, 0);
 
        /* everything below this point is Fam10h and above */
        if (boot_cpu_data.x86 == 0xf)
                return;
 
-       amd64_debug_display_dimm_sizes(1, pvt);
+       amd64_debug_display_dimm_sizes(pvt, 1);
 
        amd64_info("using %s syndromes.\n", ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
 
@@ -1226,14 +1225,13 @@ static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
 }
 
 /* Convert the sys_addr to the normalized DCT address */
-static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, int range,
+static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, unsigned range,
                                 u64 sys_addr, bool hi_rng,
                                 u32 dct_sel_base_addr)
 {
        u64 chan_off;
        u64 dram_base           = get_dram_base(pvt, range);
        u64 hole_off            = f10_dhar_offset(pvt);
-       u32 hole_valid          = dhar_valid(pvt);
        u64 dct_sel_base_off    = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
 
        if (hi_rng) {
@@ -1250,7 +1248,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, int range,
                 */
                if ((!(dct_sel_base_addr >> 16) ||
                     dct_sel_base_addr < dhar_base(pvt)) &&
-                   hole_valid &&
+                   dhar_valid(pvt) &&
                    (sys_addr >= BIT_64(32)))
                        chan_off = hole_off;
                else
@@ -1265,7 +1263,7 @@ static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, int range,
                 * else
                 *      remove dram base to normalize to DCT address
                 */
-               if (hole_valid && (sys_addr >= BIT_64(32)))
+               if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
                        chan_off = hole_off;
                else
                        chan_off = dram_base;
@@ -1381,7 +1379,7 @@ static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
 }
 
 /* For a given @dram_range, check if @sys_addr falls within it. */
-static int f1x_match_to_this_node(struct amd64_pvt *pvt, int range,
+static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
                                  u64 sys_addr, int *nid, int *chan_sel)
 {
        int cs_found = -EINVAL;
@@ -1469,7 +1467,8 @@ static int f1x_match_to_this_node(struct amd64_pvt *pvt, int range,
 static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
                                       int *node, int *chan_sel)
 {
-       int range, cs_found = -EINVAL;
+       int cs_found = -EINVAL;
+       unsigned range;
 
        for (range = 0; range < DRAM_RANGES; range++) {
 
@@ -1536,7 +1535,7 @@ static void f1x_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
  * debug routine to display the memory sizes of all logical DIMMs and its
  * CSROWs
  */
-static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
+static void amd64_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
 {
        int dimm, size0, size1, factor = 0;
        u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
@@ -1942,7 +1941,7 @@ static void read_mc_regs(struct amd64_pvt *pvt)
        struct cpuinfo_x86 *c = &boot_cpu_data;
        u64 msr_val;
        u32 tmp;
-       int range;
+       unsigned range;
 
        /*
         * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since