drm/radeon/kms/r600+: use voltage from requested clock mode (v3)

[pandora-kernel.git] / drivers / crypto / talitos.h

diff --git a/drivers/crypto/talitos.h b/drivers/crypto/talitos.h
index ff5a145..0b746ac 100644 (file)
--- a/drivers/crypto/talitos.h
+++ b/drivers/crypto/talitos.h
@@ -1,7 +1,7 @@
 /*
  * Freescale SEC (talitos) device register and descriptor header defines
  *
- * Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -130,6 +130,9 @@
 #define TALITOS_CRCUISR                        0xf030 /* cyclic redundancy check unit*/
 #define TALITOS_CRCUISR_LO             0xf034
 
+#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256      0x28
+#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512                0x48
+
 /*
  * talitos descriptor header (hdr) bits
  */
@@ -157,12 +160,16 @@
 #define        DESC_HDR_MODE0_AESU_CBC         cpu_to_be32(0x00200000)
 #define        DESC_HDR_MODE0_DEU_CBC          cpu_to_be32(0x00400000)
 #define        DESC_HDR_MODE0_DEU_3DES         cpu_to_be32(0x00200000)
+#define        DESC_HDR_MODE0_MDEU_CONT        cpu_to_be32(0x08000000)
 #define        DESC_HDR_MODE0_MDEU_INIT        cpu_to_be32(0x01000000)
 #define        DESC_HDR_MODE0_MDEU_HMAC        cpu_to_be32(0x00800000)
 #define        DESC_HDR_MODE0_MDEU_PAD         cpu_to_be32(0x00400000)
+#define        DESC_HDR_MODE0_MDEU_SHA224      cpu_to_be32(0x00300000)
 #define        DESC_HDR_MODE0_MDEU_MD5         cpu_to_be32(0x00200000)
 #define        DESC_HDR_MODE0_MDEU_SHA256      cpu_to_be32(0x00100000)
 #define        DESC_HDR_MODE0_MDEU_SHA1        cpu_to_be32(0x00000000)
+#define        DESC_HDR_MODE0_MDEUB_SHA384     cpu_to_be32(0x00000000)
+#define        DESC_HDR_MODE0_MDEUB_SHA512     cpu_to_be32(0x00200000)
 #define        DESC_HDR_MODE0_MDEU_MD5_HMAC    (DESC_HDR_MODE0_MDEU_MD5 | \
                                         DESC_HDR_MODE0_MDEU_HMAC)
 #define        DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
@@ -181,9 +188,12 @@
 #define        DESC_HDR_MODE1_MDEU_INIT        cpu_to_be32(0x00001000)
 #define        DESC_HDR_MODE1_MDEU_HMAC        cpu_to_be32(0x00000800)
 #define        DESC_HDR_MODE1_MDEU_PAD         cpu_to_be32(0x00000400)
+#define        DESC_HDR_MODE1_MDEU_SHA224      cpu_to_be32(0x00000300)
 #define        DESC_HDR_MODE1_MDEU_MD5         cpu_to_be32(0x00000200)
 #define        DESC_HDR_MODE1_MDEU_SHA256      cpu_to_be32(0x00000100)
 #define        DESC_HDR_MODE1_MDEU_SHA1        cpu_to_be32(0x00000000)
+#define        DESC_HDR_MODE1_MDEUB_SHA384     cpu_to_be32(0x00000000)
+#define        DESC_HDR_MODE1_MDEUB_SHA512     cpu_to_be32(0x00000200)
 #define        DESC_HDR_MODE1_MDEU_MD5_HMAC    (DESC_HDR_MODE1_MDEU_MD5 | \
                                         DESC_HDR_MODE1_MDEU_HMAC)
 #define        DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \