Merge branch 'x86/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip...

[pandora-kernel.git] / drivers / char / agp / amd64-agp.c

diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c
index 9e3939d..481ffe8 100644 (file)
--- a/drivers/char/agp/amd64-agp.c
+++ b/drivers/char/agp/amd64-agp.c
@@ -71,9 +71,9 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
                j++;
        }
 
-       if (mem->is_flushed == FALSE) {
+       if (!mem->is_flushed) {
                global_cache_flush();
-               mem->is_flushed = TRUE;
+               mem->is_flushed = true;
        }
 
        for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
@@ -150,25 +150,14 @@ static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
 {
        u64 aperturebase;
        u32 tmp;
-       u64 addr, aper_base;
+       u64 aper_base;
 
        /* Address to map to */
-       pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
+       pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
        aperturebase = tmp << 25;
        aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
 
-       /* address of the mappings table */
-       addr = (u64) gatt_table;
-       addr >>= 12;
-       tmp = (u32) addr<<4;
-       tmp &= ~0xf;
-       pci_write_config_dword(hammer, AMD64_GARTTABLEBASE, tmp);
-
-       /* Enable GART translation for this hammer. */
-       pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
-       tmp |= GARTEN;
-       tmp &= ~(DISGARTCPU | DISGARTIO);
-       pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
+       enable_gart_translation(hammer, gatt_table);
 
        return aper_base;
 }
@@ -207,9 +196,9 @@ static void amd64_cleanup(void)
         for (i = 0; i < num_k8_northbridges; i++) {
                struct pci_dev *dev = k8_northbridges[i];
                /* disable gart translation */
-               pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
+               pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
                tmp &= ~AMD64_GARTEN;
-               pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
+               pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
        }
 }
 
@@ -239,24 +228,10 @@ static const struct agp_bridge_driver amd_8151_driver = {
 };
 
 /* Some basic sanity checks for the aperture. */
-static int __devinit aperture_valid(u64 aper, u32 size)
+static int __devinit agp_aperture_valid(u64 aper, u32 size)
 {
-       if (aper == 0) {
-               printk(KERN_ERR PFX "No aperture\n");
-               return 0;
-       }
-       if (size < 32*1024*1024) {
-               printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
-               return 0;
-       }
-       if ((u64)aper + size > 0x100000000ULL) {
-               printk(KERN_ERR PFX "Aperture out of bounds\n");
-               return 0;
-       }
-       if (e820_any_mapped(aper, aper + size, E820_RAM)) {
-               printk(KERN_ERR PFX "Aperture pointing to RAM\n");
+       if (!aperture_valid(aper, size, 32*1024*1024))
                return 0;
-       }
 
        /* Request the Aperture. This catches cases when someone else
           already put a mapping in there - happens with some very broken BIOS
@@ -289,11 +264,11 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
        u32 nb_order, nb_base;
        u16 apsize;
 
-       pci_read_config_dword(nb, 0x90, &nb_order);
+       pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
        nb_order = (nb_order >> 1) & 7;
-       pci_read_config_dword(nb, 0x94, &nb_base);
+       pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
        nb_aper = nb_base << 25;
-       if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
+       if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
                return 0;
        }
 
@@ -317,18 +292,18 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
         * On some sick chips APSIZE is 0. This means it wants 4G
         * so let double check that order, and lets trust the AMD NB settings
         */
-       if (aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
+       if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
                printk(KERN_INFO "Aperture size %u MB is not right, using settings from NB\n",
                                  32 << order);
                order = nb_order;
        }
 
        printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
-       if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
+       if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
                return -1;
 
-       pci_write_config_dword(nb, 0x90, order << 1);
-       pci_write_config_dword(nb, 0x94, aper >> 25);
+       pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
+       pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
 
        return 0;
 }