#include <asm/io.h>
#include <asm/arch/hardware.h>
+#if !defined(CONFIG_DBGU) && !defined(CONFIG_USART0) && !defined(CONFIG_USART1)
+#error must define one of CONFIG_DBGU or CONFIG_USART0 or CONFIG_USART1
+#endif
+
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)
{
disable_interrupts();
reset_cpu(0);
#else
+#ifdef CONFIG_DBGU
+ AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;
+#endif
+#ifdef CONFIG_USART0
+ AT91PS_USART us = AT91C_BASE_US0;
+#endif
+#ifdef CONFIG_USART1
AT91PS_USART us = AT91C_BASE_US1;
+#endif
AT91PS_PIO pio = AT91C_BASE_PIOA;
/*shutdown the console to avoid strange chars during reset */
us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+#ifdef CONFIG_AT91RM9200DK
/* Clear PA19 to trigger the hard reset */
pio->PIO_CODR = 0x00080000;
pio->PIO_OER = 0x00080000;
pio->PIO_PER = 0x00080000;
+#endif
+#ifdef CONFIG_CMC_PU2
+/* this is the way Linux does it */
+#define AT91C_ST_RSTEN (0x1 << 16)
+#define AT91C_ST_EXTEN (0x1 << 17)
+#define AT91C_ST_WDRST (0x1 << 0)
+/* watchdog mode register */
+#define ST_WDMR *((unsigned long *)0xfffffd08)
+/* system clock control register */
+#define ST_CR *((unsigned long *)0xfffffd00)
+ ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+ ST_CR = AT91C_ST_WDRST;
/* Never reached */
+#endif
#endif
return 0;
}