global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[pandora-u-boot.git] / board / freescale / t208xrdb / tlb.c

diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 45c27c0..688a208 100644 (file)
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -11,31 +11,31 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+                     CFG_SYS_INIT_RAM_ADDR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                     CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                     CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-                     CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                     CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 0, BOOKE_PAGESZ_4K, 0),
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CFG_SYS_INIT_L3_ADDR)
        /*
         * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
         * SRAM is at 0xfff00000, it covered the 0xfffff000.
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+       SET_TLB_ENTRY(1, CFG_SYS_INIT_L3_ADDR, CFG_SYS_INIT_L3_ADDR,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 0, BOOKE_PAGESZ_1M, 1),
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
@@ -54,13 +54,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif
 
        /* *I*G* - CCSRBAR */
-       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 1, BOOKE_PAGESZ_16M, 1),
 
        /* *I*G* - Flash, localbus */
        /* This will be changed to *I*G* after relocation to RAM. */
-       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -92,27 +92,27 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 7, BOOKE_PAGESZ_256K, 1),
 
        /* Bman/Qman */
-#ifdef CONFIG_SYS_BMAN_MEM_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+#ifdef CFG_SYS_BMAN_MEM_PHYS
+       SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE, CFG_SYS_BMAN_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 9, BOOKE_PAGESZ_16M, 1),
-       SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
-                     CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+       SET_TLB_ENTRY(1, CFG_SYS_BMAN_MEM_BASE + 0x01000000,
+                     CFG_SYS_BMAN_MEM_PHYS + 0x01000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 10, BOOKE_PAGESZ_16M, 1),
 #endif
-#ifdef CONFIG_SYS_QMAN_MEM_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+#ifdef CFG_SYS_QMAN_MEM_PHYS
+       SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE, CFG_SYS_QMAN_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
                      0, 11, BOOKE_PAGESZ_16M, 1),
-       SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
-                     CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+       SET_TLB_ENTRY(1, CFG_SYS_QMAN_MEM_BASE + 0x01000000,
+                     CFG_SYS_QMAN_MEM_PHYS + 0x01000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
 #endif
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
-       SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+#ifdef CFG_SYS_DCSRBAR_PHYS
+       SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 13, BOOKE_PAGESZ_32M, 1),
 #endif
@@ -126,8 +126,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 16, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-       SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+#ifdef CFG_SYS_CPLD_BASE
+       SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 17, BOOKE_PAGESZ_4K, 1),
 #endif
@@ -142,7 +142,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
-       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+       SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                      0, 19, BOOKE_PAGESZ_2G, 1)
 #endif