global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[pandora-u-boot.git] / board / freescale / p1_p2_rdb_pc / tlb.c

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 4cc5e01..9477396 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -8,20 +8,20 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
-                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR,
+                       CFG_SYS_INIT_RAM_ADDR_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+                       CFG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+                       CFG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+       SET_TLB_ENTRY(0, CFG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+                       CFG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -32,14 +32,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        0, 0, BOOKE_PAGESZ_4K, 1),
 
        /* *I*G* - CCSRBAR */
-       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_CCSRBAR, CFG_SYS_CCSRBAR_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
 #ifndef CONFIG_SPL_BUILD
        /* W**G* - Flash/promjet, localbus */
        /* This will be changed to *I*G* after relocation to RAM. */
-       SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_FLASH_BASE, CFG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 2, BOOKE_PAGESZ_64M, 1),
 
@@ -57,13 +57,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifdef CONFIG_VSC7385_ENET
        /* *I*G - VSC7385 Switch */
-       SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_VSC7385_BASE, CFG_SYS_VSC7385_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 5, BOOKE_PAGESZ_1M, 1),
 #endif
 #endif /* not SPL */
 
-       SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_CPLD_BASE, CFG_SYS_CPLD_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 6, BOOKE_PAGESZ_1M, 1),
 
@@ -76,27 +76,27 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
        /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
-       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+       SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE, CFG_SYS_DDR_SDRAM_BASE,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 8, BOOKE_PAGESZ_1G, 1),
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
        /* **M** - 2G DDR on P1020MBG, map the second 1G */
-       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
-                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+       SET_TLB_ENTRY(1, CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                       CFG_SYS_DDR_SDRAM_BASE + 0x40000000,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
                        0, 9, BOOKE_PAGESZ_1G, 1),
 #endif
 #endif /* RAMBOOT/SPL */
 
-#ifdef CONFIG_SYS_INIT_L2_ADDR
+#ifdef CFG_SYS_INIT_L2_ADDR
        /* ***G - L2SRAM */
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR, CFG_SYS_INIT_L2_ADDR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 11, BOOKE_PAGESZ_256K, 1),
 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
-       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
-                     CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+       SET_TLB_ENTRY(1, CFG_SYS_INIT_L2_ADDR + 0x40000,
+                     CFG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 12, BOOKE_PAGESZ_256K, 1)
 #endif