x86: perf_counter cleanup

[pandora-kernel.git] / arch / x86 / kernel / cpu / perf_counter.c

diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 6ebe9ab..155bc3c 100644 (file)
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -17,7 +17,6 @@
 #include <linux/kdebug.h>
 #include <linux/sched.h>
 
-#include <asm/perf_counter.h>
 #include <asm/apic.h>
 
 static bool perf_counters_initialized __read_mostly;
@@ -37,7 +36,7 @@ struct cpu_hw_counters {
        unsigned long           used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
        unsigned long           interrupts;
        u64                     throttle_ctrl;
-       u64                     active_mask;
+       unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
        int                     enabled;
 };
 
@@ -291,7 +290,7 @@ static void pmc_amd_restore_all(u64 ctrl)
                return;
 
        for (idx = 0; idx < nr_counters_generic; idx++) {
-               if (test_bit(idx, (unsigned long *)&cpuc->active_mask)) {
+               if (test_bit(idx, cpuc->active_mask)) {
                        u64 val;
 
                        rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
@@ -377,7 +376,7 @@ static void pmc_amd_enable(int idx, u64 config)
 {
        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 
-       set_bit(idx, (unsigned long *)&cpuc->active_mask);
+       set_bit(idx, cpuc->active_mask);
        if (cpuc->enabled)
                config |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 
@@ -401,7 +400,7 @@ static void pmc_amd_disable(int idx, u64 config)
 {
        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
 
-       clear_bit(idx, (unsigned long *)&cpuc->active_mask);
+       clear_bit(idx, cpuc->active_mask);
        wrmsrl(MSR_K7_EVNTSEL0 + idx, config);
 
 }
@@ -954,25 +953,10 @@ static struct pmc_x86_ops *pmc_intel_init(void)
 
 static struct pmc_x86_ops *pmc_amd_init(void)
 {
-       u64 old;
-       int bits;
-
        nr_counters_generic = 4;
        nr_counters_fixed = 0;
-       counter_value_mask = ~0ULL;
-
-       rdmsrl(MSR_K7_PERFCTR0, old);
-       wrmsrl(MSR_K7_PERFCTR0, counter_value_mask);
-       /*
-        * read the truncated mask
-        */
-       rdmsrl(MSR_K7_PERFCTR0, counter_value_mask);
-       wrmsrl(MSR_K7_PERFCTR0, old);
-
-       bits = 32 + fls(counter_value_mask >> 32);
-       if (bits == 32)
-               bits = fls((u32)counter_value_mask);
-       counter_value_bits = bits;
+       counter_value_mask = 0x0000FFFFFFFFFFFFULL;
+       counter_value_bits = 48;
 
        pr_info("AMD Performance Monitoring support detected.\n");