Merge branch 'linus' into x86/irqstats

[pandora-kernel.git] / arch / x86 / kernel / cpu / cpufreq / powernow-k8.h

diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index b06c812..ab48cfe 100644 (file)
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -10,6 +10,7 @@ struct powernow_k8_data {
 
        u32 numps;  /* number of p-states */
        u32 batps;  /* number of p-states supported on battery */
+       u32 max_hw_pstate; /* maximum legal hardware pstate */
 
        /* these values are constant when the PSB is used to determine
         * vid/fid pairings, but are modified during the ->target() call
@@ -21,8 +22,8 @@ struct powernow_k8_data {
        u32 plllock; /* pll lock time, units 1 us */
         u32 exttype; /* extended interface = 1 */
 
-       /* keep track of the current fid / vid or did */
-       u32 currvid, currfid, currdid;
+       /* keep track of the current fid / vid or pstate */
+       u32 currvid, currfid, currpstate;
 
        /* the powernow_table includes all frequency and vid/fid pairings:
         * fid are the lower 8 bits of the index, vid are the upper 8 bits.
@@ -46,7 +47,7 @@ struct powernow_k8_data {
 #define CPUID_XFAM                     0x0ff00000      /* extended family */
 #define CPUID_XFAM_K8                  0
 #define CPUID_XMOD                     0x000f0000      /* extended model */
-#define CPUID_XMOD_REV_MASK            0x00080000
+#define CPUID_XMOD_REV_MASK            0x000c0000
 #define CPUID_XFAM_10H                 0x00100000      /* family 0x10 */
 #define CPUID_USE_XFAM_XMOD            0x00000f00
 #define CPUID_GET_MAX_CAPABILITIES     0x80000000
@@ -87,23 +88,14 @@ struct powernow_k8_data {
 
 /* Hardware Pstate _PSS and MSR definitions */
 #define USE_HW_PSTATE          0x00000080
-#define HW_PSTATE_FID_MASK     0x0000003f
-#define HW_PSTATE_DID_MASK     0x000001c0
-#define HW_PSTATE_DID_SHIFT    6
 #define HW_PSTATE_MASK                 0x00000007
 #define HW_PSTATE_VALID_MASK   0x80000000
-#define HW_FID_INDEX_SHIFT     8
-#define HW_FID_INDEX_MASK      0x0000ff00
-#define HW_DID_INDEX_SHIFT     16
-#define HW_DID_INDEX_MASK      0x00ff0000
-#define HW_WATTS_MASK          0xff
-#define HW_PWR_DVR_MASK                0x300
-#define HW_PWR_DVR_SHIFT       8
-#define HW_PWR_MAX_MULT                3
-#define MAX_HW_PSTATE          8       /* hw pstate supports up to 8 */
+#define HW_PSTATE_MAX_MASK     0x000000f0
+#define HW_PSTATE_MAX_SHIFT    4
 #define MSR_PSTATE_DEF_BASE    0xc0010064 /* base of Pstate MSRs */
 #define MSR_PSTATE_STATUS      0xc0010063 /* Pstate Status MSR */
 #define MSR_PSTATE_CTRL        0xc0010062 /* Pstate control MSR */
+#define MSR_PSTATE_CUR_LIMIT   0xc0010061 /* pstate current limit MSR */
 
 /* define the two driver architectures */
 #define CPU_OPTERON 0
@@ -148,10 +140,10 @@ struct powernow_k8_data {
 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
 
 #define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
-#define VST_UNITS_20US 20   /* Voltage Stabalization Time is in units of 20us */
+#define VST_UNITS_20US 20   /* Voltage Stabilization Time is in units of 20us */
 
 /*
- * Most values of interest are enocoded in a single field of the _PSS
+ * Most values of interest are encoded in a single field of the _PSS
  * entries: the "control" value.
  */