Merge git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-fixes-2.6

[pandora-kernel.git] / arch / x86 / kernel / aperture_64.c

diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index 5373f78..9f90780 100644 (file)
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -111,7 +111,7 @@ static u32 __init allocate_aperture(void)
 
 
 /* Find a PCI capability */
-static __u32 __init find_cap(int bus, int slot, int func, int cap)
+static u32 __init find_cap(int bus, int slot, int func, int cap)
 {
        int bytes;
        u8 pos;
@@ -137,7 +137,7 @@ static __u32 __init find_cap(int bus, int slot, int func, int cap)
 }
 
 /* Read a standard AGPv3 bridge header */
-static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
+static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
 {
        u32 apsize;
        u32 apsizereg;
@@ -202,7 +202,7 @@ static __u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
  * the AGP bridges should be always an own bus on the HT hierarchy,
  * but do it here for future safety.
  */
-static __u32 __init search_agp_bridge(u32 *order, int *valid_agp)
+static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
 {
        int bus, slot, func;
 
@@ -271,16 +271,16 @@ void __init early_gart_iommu_check(void)
         * or BIOS forget to put that in reserved.
         * try to update e820 to make that region as reserved.
         */
-       int fix, slot;
+       int i, fix, slot;
        u32 ctl;
        u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
        u64 aper_base = 0, last_aper_base = 0;
-       int aper_enabled = 0, last_aper_enabled = 0;
-       int i;
+       int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
 
        if (!early_pci_allowed())
                return;
 
+       /* This is mostly duplicate of iommu_hole_init */
        fix = 0;
        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
                int bus;
@@ -301,19 +301,22 @@ void __init early_gart_iommu_check(void)
                        aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
                        aper_base <<= 25;
 
-                       if ((last_aper_order && aper_order != last_aper_order) ||
-                           (last_aper_base && aper_base != last_aper_base) ||
-                           (last_aper_enabled && aper_enabled != last_aper_enabled)) {
-                               fix = 1;
-                               goto out;
+                       if (last_valid) {
+                               if ((aper_order != last_aper_order) ||
+                                   (aper_base != last_aper_base) ||
+                                   (aper_enabled != last_aper_enabled)) {
+                                       fix = 1;
+                                       break;
+                               }
                        }
+
                        last_aper_order = aper_order;
                        last_aper_base = aper_base;
                        last_aper_enabled = aper_enabled;
+                       last_valid = 1;
                }
        }
 
-out:
        if (!fix && !aper_enabled)
                return;
 
@@ -321,16 +324,18 @@ out:
                fix = 1;
 
        if (gart_fix_e820 && !fix && aper_enabled) {
-               if (!e820_all_mapped(aper_base, aper_base + aper_size,
-                                   E820_RESERVED)) {
+               if (e820_any_mapped(aper_base, aper_base + aper_size,
+                                   E820_RAM)) {
                        /* reserve it, so we can reuse it in second kernel */
                        printk(KERN_INFO "update e820 for GART\n");
-                       add_memory_region(aper_base, aper_size, E820_RESERVED);
+                       e820_add_region(aper_base, aper_size, E820_RESERVED);
                        update_e820();
                }
-               return;
        }
 
+       if (!fix)
+               return;
+
        /* different nodes have different setting, disable them all at first*/
        for (i = 0; i < ARRAY_SIZE(bus_dev_ranges); i++) {
                int bus;
@@ -402,7 +407,9 @@ void __init gart_iommu_hole_init(void)
                                    agp_aper_base == aper_base &&
                                    agp_aper_order == aper_order) {
                                        /* the same between two setting from NB and agp */
-                                       if (!no_iommu && end_pfn > MAX_DMA32_PFN && !printed_gart_size_msg) {
+                                       if (!no_iommu &&
+                                           max_pfn > MAX_DMA32_PFN &&
+                                           !printed_gart_size_msg) {
                                                printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
                                                printk(KERN_ERR "please increase GART size in your BIOS setup\n");
                                                printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
@@ -443,7 +450,7 @@ out:
                /* Got the aperture from the AGP bridge */
        } else if (swiotlb && !valid_agp) {
                /* Do nothing */
-       } else if ((!no_iommu && end_pfn > MAX_DMA32_PFN) ||
+       } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
                   force_iommu ||
                   valid_agp ||
                   fallback_aper_force) {
@@ -491,4 +498,6 @@ out:
                        write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
                }
        }
+
+       set_up_gart_resume(aper_order, aper_alloc);
 }