Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-serial

[pandora-kernel.git] / arch / sparc64 / lib / VISsave.S

diff --git a/arch/sparc64/lib/VISsave.S b/arch/sparc64/lib/VISsave.S
index 4e18989..a0ded5c 100644 (file)
--- a/arch/sparc64/lib/VISsave.S
+++ b/arch/sparc64/lib/VISsave.S
@@ -59,15 +59,17 @@ vis1:       ldub            [%g6 + TI_FPSAVED], %g3
        be,pn           %icc, 9b
         add            %g6, TI_FPREGS, %g2
        andcc           %o5, FPRS_DL, %g0
-       membar          #StoreStore | #LoadStore
 
        be,pn           %icc, 4f
         add            %g6, TI_FPREGS+0x40, %g3
+       membar          #Sync
        stda            %f0, [%g2 + %g1] ASI_BLK_P
        stda            %f16, [%g3 + %g1] ASI_BLK_P
+       membar          #Sync
        andcc           %o5, FPRS_DU, %g0
        be,pn           %icc, 5f
 4:      add            %g1, 128, %g1
+       membar          #Sync
        stda            %f32, [%g2 + %g1] ASI_BLK_P
 
        stda            %f48, [%g3 + %g1] ASI_BLK_P
@@ -87,7 +89,7 @@ vis1: ldub            [%g6 + TI_FPSAVED], %g3
        sll             %g1, 5, %g1
        add             %g6, TI_FPREGS+0xc0, %g3
        wr              %g0, FPRS_FEF, %fprs
-       membar          #StoreStore | #LoadStore
+       membar          #Sync
        stda            %f32, [%g2 + %g1] ASI_BLK_P
        stda            %f48, [%g3 + %g1] ASI_BLK_P
        membar          #Sync
@@ -128,8 +130,8 @@ VISenterhalf:
        be,pn           %icc, 4f
         add            %g6, TI_FPREGS, %g2
 
-       membar          #StoreStore | #LoadStore
        add             %g6, TI_FPREGS+0x40, %g3
+       membar          #Sync
        stda            %f0, [%g2 + %g1] ASI_BLK_P
        stda            %f16, [%g3 + %g1] ASI_BLK_P
        membar          #Sync