sh: Mass ctrl_in/outX to __raw_read/writeX conversion.

[pandora-kernel.git] / arch / sh / mm / tlb-sh4.c

diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 624c1da..ccac77f 100644 (file)
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -29,7 +29,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 
        /* Set PTEH register */
        vpn = (address & MMU_VPN_MASK) | get_asid();
-       ctrl_outl(vpn, MMU_PTEH);
+       __raw_writel(vpn, MMU_PTEH);
 
        pteval = pte.pte_low;
 
@@ -41,13 +41,13 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
         * the protection bits (with the exception of the compat-mode SZ
         * and PR bits, which are cleared) being written out in PTEL.
         */
-       ctrl_outl(pte.pte_high, MMU_PTEA);
+       __raw_writel(pte.pte_high, MMU_PTEA);
 #else
        if (cpu_data->flags & CPU_HAS_PTEA) {
                /* The last 3 bits and the first one of pteval contains
                 * the PTEA timing control and space attribute bits
                 */
-               ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA);
+               __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
        }
 #endif
 
@@ -57,7 +57,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
        pteval |= _PAGE_WT;
 #endif
        /* conveniently, we want all the software flags to be 0 anyway */
-       ctrl_outl(pteval, MMU_PTEL);
+       __raw_writel(pteval, MMU_PTEL);
 
        /* Load the TLB */
        asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -77,6 +77,6 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
        addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
        data = page | asid; /* VALID bit is off */
        jump_to_uncached();
-       ctrl_outl(data, addr);
+       __raw_writel(data, addr);
        back_to_cached();
 }