Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

[pandora-kernel.git] / arch / sh / mm / Kconfig

diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 0c24abd..70da1c8 100644 (file)
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -36,6 +36,9 @@ config CPU_SUBTYPE_ST40
 config CPU_SHX2
        bool
 
+config CPU_SHX3
+       bool
+
 choice
        prompt "Processor sub-type selection"
 
@@ -45,13 +48,10 @@ choice
 
 # SH-2 Processor Support
 
-config CPU_SUBTYPE_SH7604
-       bool "Support SH7604 processor"
-       select CPU_SH2
-
 config CPU_SUBTYPE_SH7619
        bool "Support SH7619 processor"
        select CPU_SH2
+       select CPU_HAS_IPR_IRQ
 
 # SH-2A Processor Support
 
@@ -120,13 +120,14 @@ config CPU_SUBTYPE_SH7712
 config CPU_SUBTYPE_SH7750
        bool "Support SH7750 processor"
        select CPU_SH4
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
        help
          Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
 
 config CPU_SUBTYPE_SH7091
        bool "Support SH7091 processor"
        select CPU_SH4
+       select CPU_HAS_INTC_IRQ
        help
          Select SH7091 if you have an SH-4 based Sega device (such as
          the Dreamcast, Naomi, and Naomi 2).
@@ -134,17 +135,17 @@ config CPU_SUBTYPE_SH7091
 config CPU_SUBTYPE_SH7750R
        bool "Support SH7750R processor"
        select CPU_SH4
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
 
 config CPU_SUBTYPE_SH7750S
        bool "Support SH7750S processor"
        select CPU_SH4
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
 
 config CPU_SUBTYPE_SH7751
        bool "Support SH7751 processor"
        select CPU_SH4
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
        help
          Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
          or if you have a HD6417751R CPU.
@@ -152,7 +153,7 @@ config CPU_SUBTYPE_SH7751
 config CPU_SUBTYPE_SH7751R
        bool "Support SH7751R processor"
        select CPU_SH4
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
 
 config CPU_SUBTYPE_SH7760
        bool "Support SH7760 processor"
@@ -188,7 +189,7 @@ config CPU_SUBTYPE_SH7770
 config CPU_SUBTYPE_SH7780
        bool "Support SH7780 processor"
        select CPU_SH4A
-       select CPU_HAS_INTC2_IRQ
+       select CPU_HAS_INTC_IRQ
 
 config CPU_SUBTYPE_SH7785
        bool "Support SH7785 processor"
@@ -196,6 +197,12 @@ config CPU_SUBTYPE_SH7785
        select CPU_SHX2
        select CPU_HAS_INTC2_IRQ
 
+config CPU_SUBTYPE_SHX3
+       bool "Support SH-X3 processor"
+       select CPU_SH4A
+       select CPU_SHX3
+       select CPU_HAS_INTC2_IRQ
+
 # SH4AL-DSP Processor Support
 
 config CPU_SUBTYPE_SH73180
@@ -210,8 +217,9 @@ config CPU_SUBTYPE_SH7722
        bool "Support SH7722 processor"
        select CPU_SH4AL_DSP
        select CPU_SHX2
-       select CPU_HAS_IPR_IRQ
+       select CPU_HAS_INTC_IRQ
        select ARCH_SPARSEMEM_ENABLE
+       select SYS_SUPPORTS_NUMA
 
 endchoice
 
@@ -265,7 +273,7 @@ config MEMORY_SIZE
 
 config 32BIT
        bool "Support 32-bit physical addressing through PMB"
-       depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
+       depends on MMU && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
        default y
        help
          If you say Y here, physical addressing will be extended to
@@ -296,7 +304,7 @@ config VSYSCALL
 
 config NUMA
        bool "Non Uniform Memory Access (NUMA) Support"
-       depends on MMU && SPARSEMEM && EXPERIMENTAL
+       depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
        default n
        help
          Some SH systems have many various memories scattered around
@@ -312,6 +320,7 @@ config NODES_SHIFT
 
 config ARCH_FLATMEM_ENABLE
        def_bool y
+       depends on !NUMA
 
 config ARCH_SPARSEMEM_ENABLE
        def_bool y
@@ -423,15 +432,4 @@ config SH_WRITETHROUGH
 
          If unsure, say N.
 
-config SH_OCRAM
-       bool "Operand Cache RAM (OCRAM) support"
-       help
-         Selecting this option will automatically tear down the number of
-         sets in the dcache by half, which in turn exposes a memory range.
-
-         The addresses for the OC RAM base will vary according to the
-         processor version. Consult vendor documentation for specifics.
-
-         If unsure, say N.
-
 endmenu