Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm

[pandora-kernel.git] / arch / sh / kernel / cpu / sh4a / setup-sh7722.c

diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index d551ed8..5813d80 100644 (file)
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -181,6 +181,8 @@ struct platform_device dma_device = {
 static struct plat_sci_port scif0_platform_data = {
        .mapbase        = 0xffe00000,
        .flags          = UPF_BOOT_AUTOCONF,
+       .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+       .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
        .irqs           = { 80, 80, 80, 80 },
 };
@@ -196,6 +198,8 @@ static struct platform_device scif0_device = {
 static struct plat_sci_port scif1_platform_data = {
        .mapbase        = 0xffe10000,
        .flags          = UPF_BOOT_AUTOCONF,
+       .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+       .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
        .irqs           = { 81, 81, 81, 81 },
 };
@@ -211,6 +215,8 @@ static struct platform_device scif1_device = {
 static struct plat_sci_port scif2_platform_data = {
        .mapbase        = 0xffe20000,
        .flags          = UPF_BOOT_AUTOCONF,
+       .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
+       .scbrr_algo_id  = SCBRR_ALGO_2,
        .type           = PORT_SCIF,
        .irqs           = { 82, 82, 82, 82 },
 };
@@ -699,7 +705,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
          { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
        { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-         { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
+         { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
        { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
          { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
        { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */