*
* SH7785 support for the clock framework
*
- * Copyright (C) 2007 Paul Mundt
+ * Copyright (C) 2007 - 2009 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
*/
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cpufreq.h>
#include <asm/clock.h>
#include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4, 6 };
-static int ufc_divisors[] = { 1, 1, 4, 6 };
-static int sfc_divisors[] = { 1, 1, 4, 6 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
- 24, 32, 36, 48, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 6 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
- 24, 32, 36, 48, 1, 1, 1, 1 };
-
-static void master_clk_init(struct clk *clk)
-{
- clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
-static struct clk_ops sh7785_master_clk_ops = {
- .init = master_clk_init,
-};
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+ 24, 32, 36, 48 };
+struct clk_priv {
+ unsigned int shift;
-static void module_clk_recalc(struct clk *clk)
-{
- int idx = (ctrl_inl(FRQMR1) & 0x000f);
- clk->rate = clk->parent->rate / pfc_divisors[idx];
-}
+ /* allowable divisor bitmap */
+ unsigned long div_bitmap;
-static struct clk_ops sh7785_module_clk_ops = {
- .recalc = module_clk_recalc,
+ /* Supportable frequencies + termination entry */
+ struct cpufreq_frequency_table freq_table[ARRAY_SIZE(div2)+1];
};
-static void bus_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
- clk->rate = clk->parent->rate / bfc_divisors[idx];
+#define FRQMR_CLK_DATA(_name, _shift, _div_bitmap) \
+static struct clk_priv _name##_data = { \
+ .shift = _shift, \
+ .div_bitmap = _div_bitmap, \
+ \
+ .freq_table[0] = { \
+ .index = 0, \
+ .frequency = CPUFREQ_TABLE_END, \
+ }, \
}
-static struct clk_ops sh7785_bus_clk_ops = {
- .recalc = bus_clk_recalc,
-};
+FRQMR_CLK_DATA(pfc, 0, 0x0f80);
+FRQMR_CLK_DATA(s3fc, 4, 0x0ff0);
+FRQMR_CLK_DATA(s2fc, 8, 0x0030);
+FRQMR_CLK_DATA(mfc, 12, 0x000c);
+FRQMR_CLK_DATA(bfc, 16, 0x0fe0);
+FRQMR_CLK_DATA(sfc, 20, 0x000c);
+FRQMR_CLK_DATA(ufc, 24, 0x000c);
+FRQMR_CLK_DATA(ifc, 28, 0x000e);
-static void cpu_clk_recalc(struct clk *clk)
+static unsigned long frqmr_recalc(struct clk *clk)
{
- int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
- clk->rate = clk->parent->rate / ifc_divisors[idx];
-}
+ struct clk_priv *data = clk->priv;
+ unsigned int idx;
-static struct clk_ops sh7785_cpu_clk_ops = {
- .recalc = cpu_clk_recalc,
-};
+ idx = (__raw_readl(FRQMR1) >> data->shift) & 0x000f;
-static struct clk_ops *sh7785_clk_ops[] = {
- &sh7785_master_clk_ops,
- &sh7785_module_clk_ops,
- &sh7785_bus_clk_ops,
- &sh7785_cpu_clk_ops,
-};
+ /*
+ * XXX: PLL1 multiplier is locked for the default clock mode,
+ * when mode pin detection and configuration support is added,
+ * select the multiplier dynamically.
+ */
+ return clk->parent->rate * 36 / div2[idx];
+}
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+static void frqmr_build_rate_table(struct clk *clk)
{
- if (idx < ARRAY_SIZE(sh7785_clk_ops))
- *ops = sh7785_clk_ops[idx];
+ struct clk_priv *data = clk->priv;
+ int i, entry;
+
+ for (i = entry = 0; i < ARRAY_SIZE(div2); i++) {
+ if ((data->div_bitmap & (1 << i)) == 0)
+ continue;
+
+ data->freq_table[entry].index = entry;
+ data->freq_table[entry].frequency =
+ clk->parent->rate * 36 / div2[i];
+
+ entry++;
+ }
+
+ if (entry == 0) {
+ pr_warning("clkfwk: failed to build frequency table "
+ "for \"%s\" clk!\n", clk->name);
+ return;
+ }
+
+ /* Termination entry */
+ data->freq_table[entry].index = entry;
+ data->freq_table[entry].frequency = CPUFREQ_TABLE_END;
}
-static void shyway_clk_recalc(struct clk *clk)
+static long frqmr_round_rate(struct clk *clk, unsigned long rate)
{
- int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
- clk->rate = clk->parent->rate / sfc_divisors[idx];
+ struct clk_priv *data = clk->priv;
+ unsigned long rate_error, rate_error_prev = ~0UL;
+ unsigned long rate_best_fit = rate;
+ unsigned long highest, lowest;
+ int i;
+
+ highest = lowest = 0;
+
+ for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
+ unsigned long freq = data->freq_table[i].frequency;
+
+ if (freq == CPUFREQ_ENTRY_INVALID)
+ continue;
+
+ if (freq > highest)
+ highest = freq;
+ if (freq < lowest)
+ lowest = freq;
+
+ rate_error = abs(freq - rate);
+ if (rate_error < rate_error_prev) {
+ rate_best_fit = freq;
+ rate_error_prev = rate_error;
+ }
+
+ if (rate_error == 0)
+ break;
+ }
+
+ if (rate >= highest)
+ rate_best_fit = highest;
+ if (rate <= lowest)
+ rate_best_fit = lowest;
+
+ return rate_best_fit;
}
-static struct clk_ops sh7785_shyway_clk_ops = {
- .recalc = shyway_clk_recalc,
+static struct clk_ops frqmr_clk_ops = {
+ .recalc = frqmr_recalc,
+ .build_rate_table = frqmr_build_rate_table,
+ .round_rate = frqmr_round_rate,
};
-static struct clk sh7785_shyway_clk = {
- .name = "shyway_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_shyway_clk_ops,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+ .name = "extal",
+ .id = -1,
+ .rate = 33333333,
};
-static void ddr_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
- clk->rate = clk->parent->rate / mfc_divisors[idx];
-}
-
-static struct clk_ops sh7785_ddr_clk_ops = {
- .recalc = ddr_clk_recalc,
+static struct clk cpu_clk = {
+ .name = "cpu_clk", /* Ick */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &ifc_data,
};
-static struct clk sh7785_ddr_clk = {
- .name = "ddr_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_ddr_clk_ops,
+static struct clk shyway_clk = {
+ .name = "shyway_clk", /* SHck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &sfc_data,
};
-static void ram_clk_recalc(struct clk *clk)
-{
- int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003);
- clk->rate = clk->parent->rate / ufc_divisors[idx];
-}
+static struct clk peripheral_clk = {
+ .name = "peripheral_clk", /* Pck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &pfc_data,
+};
-static struct clk_ops sh7785_ram_clk_ops = {
- .recalc = ram_clk_recalc,
+static struct clk ddr_clk = {
+ .name = "ddr_clk", /* DDRck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &mfc_data,
};
-static struct clk sh7785_ram_clk = {
- .name = "ram_clk",
- .flags = CLK_ALWAYS_ENABLED,
- .ops = &sh7785_ram_clk_ops,
+static struct clk bus_clk = {
+ .name = "bus_clk", /* Bck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &bfc_data,
};
-/*
- * Additional SH7785-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7785_onchip_clocks[] = {
- &sh7785_shyway_clk,
- &sh7785_ddr_clk,
- &sh7785_ram_clk,
+static struct clk ga_clk = {
+ .name = "ga_clk", /* GAck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .priv = &s2fc_data,
};
-static int __init sh7785_clk_init(void)
-{
- struct clk *clk = clk_get(NULL, "master_clk");
- int i;
+static struct clk du_clk = {
+ .name = "du_clk", /* DUck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .priv = &s3fc_data,
+};
- for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
- struct clk *clkp = sh7785_onchip_clocks[i];
+static struct clk umem_clk = {
+ .name = "umem_clk", /* uck */
+ .id = -1,
+ .ops = &frqmr_clk_ops,
+ .parent = &extal_clk,
+ .flags = CLK_ENABLE_ON_INIT,
+ .priv = &ufc_data,
+};
- clkp->parent = clk;
- clk_register(clkp);
- clk_enable(clkp);
- }
+static struct clk *clks[] = {
+ &extal_clk,
+ &cpu_clk,
+ ­way_clk,
+ &peripheral_clk,
+ &ddr_clk,
+ &bus_clk,
+ &ga_clk,
+ &du_clk,
+ &umem_clk,
+};
- /*
- * Now that we have the rest of the clocks registered, we need to
- * force the parent clock to propagate so that these clocks will
- * automatically figure out their rate. We cheat by handing the
- * parent clock its current rate and forcing child propagation.
- */
- clk_set_rate(clk, clk_get_rate(clk));
+int __init arch_clk_init(void)
+{
+ int i, ret = 0;
- clk_put(clk);
+ for (i = 0; i < ARRAY_SIZE(clks); i++)
+ ret |= clk_register(clks[i]);
- return 0;
+ return ret;
}
-arch_initcall(sh7785_clk_init);
git.openpandora.org / pandora-kernel.git / blobdiff