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[PATCH] ppc32: Add cputable entry for 750CXe DD2.4 ("Gekko")
[pandora-kernel.git] / arch / ppc / kernel / cputable.c
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c
index d44b7dc..fa6df9d 100644 (file)
--- a/arch/ppc/kernel/cputable.c
+++ b/arch/ppc/kernel/cputable.c
@@ -198,10 +198,10 @@ struct cpu_spec   cpu_specs[] = {
                .num_pmcs               = 4,
                .cpu_setup              = __setup_cpu_750
        },
-       {       /* 745/755 */
-               .pvr_mask               = 0xfffff000,
-               .pvr_value              = 0x00083000,
-               .cpu_name               = "745/755",
+       {       /* 750CX (80100 and 8010x?) */
+               .pvr_mask               = 0xfffffff0,
+               .pvr_value              = 0x00080100,
+               .cpu_name               = "750CX",
                .cpu_features           = CPU_FTR_COMMON |
                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
                        CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
@@ -210,11 +210,11 @@ struct cpu_spec   cpu_specs[] = {
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
                .num_pmcs               = 4,
-               .cpu_setup              = __setup_cpu_750
+               .cpu_setup              = __setup_cpu_750cx
        },
-       {       /* 750CX (80100 and 8010x?) */
+       {       /* 750CX (82201 and 82202) */
                .pvr_mask               = 0xfffffff0,
-               .pvr_value              = 0x00080100,
+               .pvr_value              = 0x00082200,
                .cpu_name               = "750CX",
                .cpu_features           = CPU_FTR_COMMON |
                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
@@ -226,10 +226,10 @@ struct cpu_spec   cpu_specs[] = {
                .num_pmcs               = 4,
                .cpu_setup              = __setup_cpu_750cx
        },
-       {       /* 750CX (82201 and 82202) */
+       {       /* 750CXe (82214) */
                .pvr_mask               = 0xfffffff0,
-               .pvr_value              = 0x00082200,
-               .cpu_name               = "750CX",
+               .pvr_value              = 0x00082210,
+               .cpu_name               = "750CXe",
                .cpu_features           = CPU_FTR_COMMON |
                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
                        CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
@@ -240,9 +240,9 @@ struct cpu_spec     cpu_specs[] = {
                .num_pmcs               = 4,
                .cpu_setup              = __setup_cpu_750cx
        },
-       {       /* 750CXe (82214) */
-               .pvr_mask               = 0xfffffff0,
-               .pvr_value              = 0x00082210,
+       {       /* 750CXe "Gekko" (83214) */
+               .pvr_mask               = 0xffffffff,
+               .pvr_value              = 0x00083214,
                .cpu_name               = "750CXe",
                .cpu_features           = CPU_FTR_COMMON |
                        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
@@ -254,6 +254,20 @@ struct cpu_spec    cpu_specs[] = {
                .num_pmcs               = 4,
                .cpu_setup              = __setup_cpu_750cx
        },
+       {       /* 745/755 */
+               .pvr_mask               = 0xfffff000,
+               .pvr_value              = 0x00083000,
+               .cpu_name               = "745/755",
+               .cpu_features           = CPU_FTR_COMMON |
+                       CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
+                       CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
+                       CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
+               .cpu_user_features      = COMMON_PPC,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+               .num_pmcs               = 4,
+               .cpu_setup              = __setup_cpu_750
+       },
        {       /* 750FX rev 1.x */
                .pvr_mask               = 0xffffff00,
                .pvr_value              = 0x70000100,
@@ -852,6 +866,26 @@ struct cpu_spec    cpu_specs[] = {
 
 #endif /* CONFIG_40x */
 #ifdef CONFIG_44x
+       {
+               .pvr_mask               = 0xf0000fff,
+               .pvr_value              = 0x40000850,
+               .cpu_name               = "440EP Rev. A",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB,
+               .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+       },
+       {
+               .pvr_mask               = 0xf0000fff,
+               .pvr_value              = 0x400008d3,
+               .cpu_name               = "440EP Rev. B",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB,
+               .cpu_user_features      = COMMON_PPC, /* 440EP has an FPU */
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+       },
        {       /* 440GP Rev. B */
                .pvr_mask               = 0xf0000fff,
                .pvr_value              = 0x40000440,
@@ -902,8 +936,51 @@ struct cpu_spec    cpu_specs[] = {
                .icache_bsize           = 32,
                .dcache_bsize           = 32,
        },
+       { /* 440GX Rev. F */
+               .pvr_mask               = 0xf0000fff,
+               .pvr_value              = 0x50000894,
+               .cpu_name               = "440GX Rev. F",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB,
+               .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+       },
+       { /* 440SP Rev. A */
+               .pvr_mask               = 0xff000fff,
+               .pvr_value              = 0x53000891,
+               .cpu_name               = "440SP Rev. A",
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB,
+               .cpu_user_features      = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+       },
 #endif /* CONFIG_44x */
-#ifdef CONFIG_E500
+#ifdef CONFIG_FSL_BOOKE
+       {       /* e200z5 */
+               .pvr_mask               = 0xfff00000,
+               .pvr_value              = 0x81000000,
+               .cpu_name               = "e200z5",
+               /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
+               .cpu_features           = CPU_FTR_USE_TB,
+               .cpu_user_features      = PPC_FEATURE_32 |
+                       PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
+                       PPC_FEATURE_UNIFIED_CACHE,
+               .dcache_bsize           = 32,
+       },
+       {       /* e200z6 */
+               .pvr_mask               = 0xfff00000,
+               .pvr_value              = 0x81100000,
+               .cpu_name               = "e200z6",
+               /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
+               .cpu_features           = CPU_FTR_USE_TB,
+               .cpu_user_features      = PPC_FEATURE_32 |
+                       PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
+                       PPC_FEATURE_HAS_EFP_SINGLE |
+                       PPC_FEATURE_UNIFIED_CACHE,
+               .dcache_bsize           = 32,
+       },
        {       /* e500 */
                .pvr_mask               = 0xffff0000,
                .pvr_value              = 0x80200000,
@@ -918,6 +995,20 @@ struct cpu_spec    cpu_specs[] = {
                .dcache_bsize           = 32,
                .num_pmcs               = 4,
        },
+       {       /* e500v2 */
+               .pvr_mask               = 0xffff0000,
+               .pvr_value              = 0x80210000,
+               .cpu_name               = "e500v2",
+               /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
+               .cpu_features           = CPU_FTR_SPLIT_ID_CACHE |
+                       CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
+               .cpu_user_features      = PPC_FEATURE_32 |
+                       PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
+                       PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
+               .icache_bsize           = 32,
+               .dcache_bsize           = 32,
+               .num_pmcs               = 4,
+       },
 #endif
 #if !CLASSIC_PPC
        {       /* default match */
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