Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq

[pandora-kernel.git] / arch / powerpc / mm / 44x_mmu.c

diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 376829e..98052ac 100644 (file)
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -12,7 +12,6 @@
  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  *    Copyright (C) 1996 Paul Mackerras
- *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  *
  *  Derived from "arch/i386/mm/init.c"
  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
@@ -24,96 +23,80 @@
  *
  */
 
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/ptrace.h>
-#include <linux/mman.h>
-#include <linux/mm.h>
-#include <linux/swap.h>
-#include <linux/stddef.h>
-#include <linux/vmalloc.h>
 #include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/highmem.h>
-
-#include <asm/pgalloc.h>
-#include <asm/prom.h>
-#include <asm/io.h>
-#include <asm/mmu_context.h>
-#include <asm/pgtable.h>
 #include <asm/mmu.h>
-#include <asm/uaccess.h>
-#include <asm/smp.h>
-#include <asm/bootx.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
+#include <asm/system.h>
+#include <asm/page.h>
+#include <asm/cacheflush.h>
 
 #include "mmu_decl.h"
 
-extern char etext[], _stext[];
-
 /* Used by the 44x TLB replacement exception handler.
  * Just needed it declared someplace.
  */
-unsigned int tlb_44x_index = 0;
-unsigned int tlb_44x_hwater = 62;
+unsigned int tlb_44x_index; /* = 0 */
+unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
+int icache_44x_need_flush;
+
+static void __init ppc44x_update_tlb_hwater(void)
+{
+       extern unsigned int tlb_44x_patch_hwater_D[];
+       extern unsigned int tlb_44x_patch_hwater_I[];
+
+       /* The TLB miss handlers hard codes the watermark in a cmpli
+        * instruction to improve performances rather than loading it
+        * from the global variable. Thus, we patch the instructions
+        * in the 2 TLB miss handlers when updating the value
+        */
+       tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
+               tlb_44x_hwater;
+       flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
+                          (unsigned long)&tlb_44x_patch_hwater_D[1]);
+       tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
+               tlb_44x_hwater;
+       flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
+                          (unsigned long)&tlb_44x_patch_hwater_I[1]);
+}
 
 /*
  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
  */
-static void __init
-ppc44x_pin_tlb(int slot, unsigned int virt, unsigned int phys)
+static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
 {
-       unsigned long attrib = 0;
+       unsigned int entry = tlb_44x_hwater--;
 
-       __asm__ __volatile__("\
-       clrrwi  %2,%2,10\n\
-       ori     %2,%2,%4\n\
-       clrrwi  %1,%1,10\n\
-       li      %0,0\n\
-       ori     %0,%0,%5\n\
-       tlbwe   %2,%3,%6\n\
-       tlbwe   %1,%3,%7\n\
-       tlbwe   %0,%3,%8"
+       ppc44x_update_tlb_hwater();
+
+       __asm__ __volatile__(
+               "tlbwe  %2,%3,%4\n"
+               "tlbwe  %1,%3,%5\n"
+               "tlbwe  %0,%3,%6\n"
        :
-       : "r" (attrib), "r" (phys), "r" (virt), "r" (slot),
-         "i" (PPC44x_TLB_VALID | PPC44x_TLB_256M),
-         "i" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+       : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
+         "r" (phys),
+         "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
+         "r" (entry),
          "i" (PPC44x_TLB_PAGEID),
          "i" (PPC44x_TLB_XLAT),
          "i" (PPC44x_TLB_ATTRIB));
 }
 
-/*
- * MMU_init_hw does the chip-specific initialization of the MMU hardware.
- */
 void __init MMU_init_hw(void)
 {
+       ppc44x_update_tlb_hwater();
+
        flush_instruction_cache();
 }
 
 unsigned long __init mmu_mapin_ram(void)
 {
-       unsigned int pinned_tlbs = 1;
-       int i;
-
-       /* Determine number of entries necessary to cover lowmem */
-       pinned_tlbs = (unsigned int)
-               (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT);
-
-       /* Write upper watermark to save location */
-       tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
+       unsigned long addr;
 
-       /* If necessary, set additional pinned TLBs */
-       if (pinned_tlbs > 1)
-               for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
-                       unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE;
-                       ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
-               }
+       /* Pin in enough TLBs to cover any lowmem not covered by the
+        * initial 256M mapping established in head_44x.S */
+       for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
+            addr += PPC_PIN_SIZE)
+               ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 
        return total_lowmem;
 }