powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

[pandora-u-boot.git] / arch / powerpc / cpu / mpc85xx / tlb.c

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 01a3561..a548dec 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 
 void disable_tlb(u8 esel)
 {
-       u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+       u32 _mas0, _mas1, _mas2, _mas3;
 
        free_tlb_cam(esel);
 
@@ -180,14 +180,13 @@ void disable_tlb(u8 esel)
        _mas1 = 0;
        _mas2 = 0;
        _mas3 = 0;
-       _mas7 = 0;
 
        mtspr(MAS0, _mas0);
        mtspr(MAS1, _mas1);
        mtspr(MAS2, _mas2);
        mtspr(MAS3, _mas3);
 #ifdef CONFIG_ENABLE_36BIT_PHYS
-       mtspr(MAS7, _mas7);
+       mtspr(MAS7, 0);
 #endif
        asm volatile("isync;msync;tlbwe;isync");
 
@@ -250,18 +249,22 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
        int i;
        unsigned int tlb_size;
-       unsigned int wimge = 0;
+       unsigned int wimge = MAS2_M;
        unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-       unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+       unsigned int max_cam;
        u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
        wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
        size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
-       /* Convert (4^max) kB to (2^max) bytes */
-       max_cam = max_cam * 2 + 10;
+       if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+               /* Convert (4^max) kB to (2^max) bytes */
+               max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+       } else {
+               /* Convert (2^max) kB to (2^max) bytes */
+               max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+       }
 
        for (i = 0; size && i < 8; i++) {
                int ram_tlb_index = find_free_tlbcam();