Merge git://git.infradead.org/mtd-2.6

[pandora-kernel.git] / arch / powerpc / boot / 4xx.c

diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c
index 1a83efe..5c87843 100644 (file)
--- a/arch/powerpc/boot/4xx.c
+++ b/arch/powerpc/boot/4xx.c
@@ -21,6 +21,25 @@
 #include "reg.h"
 #include "dcr.h"
 
+static unsigned long chip_11_errata(unsigned long memsize)
+{
+       unsigned long pvr;
+
+       pvr = mfpvr();
+
+       switch (pvr & 0xf0000ff0) {
+               case 0x40000850:
+               case 0x400008d0:
+               case 0x200008d0:
+                       memsize -= 4096;
+                       break;
+               default:
+                       break;
+       }
+
+       return memsize;
+}
+
 /* Read the 4xx SDRAM controller to get size of system memory. */
 void ibm4xx_sdram_fixup_memsize(void)
 {
@@ -34,6 +53,7 @@ void ibm4xx_sdram_fixup_memsize(void)
                        memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
        }
 
+       memsize = chip_11_errata(memsize);
        dt_fixup_memory(0, memsize);
 }
 
@@ -159,7 +179,7 @@ void ibm4xx_denali_fixup_memsize(void)
        val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
        cs = 0;
        while (val) {
-               if (val && 0x1)
+               if (val & 0x1)
                        cs++;
                val = val >> 1;
        }
@@ -199,6 +219,7 @@ void ibm4xx_denali_fixup_memsize(void)
                bank = 4; /* 4 banks */
 
        memsize = cs * (1 << (col+row)) * bank * dpath;
+       memsize = chip_11_errata(memsize);
        dt_fixup_memory(0, memsize);
 }
 
@@ -243,7 +264,8 @@ void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
                *emac1 = EMAC_RESET;
 
        mtdcr(DCRN_MAL0_CFG, MAL_RESET);
-       while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) {};
+       while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
+               ; /* loop until reset takes effect */
 }
 
 /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
@@ -498,36 +520,59 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
        u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
        u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
        u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
+       u32 psr = mfdcr(DCRN_405_CPC0_PSR);
        u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
-       u32 fwdv, fbdv, cbdv, opdv, epdv, udiv;
+       u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
 
        fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
        fbdv = (pllmr & 0x1e000000) >> 25;
-       cbdv = ((pllmr & 0x00060000) >> 17) + 1;
-       opdv = ((pllmr & 0x00018000) >> 15) + 1;
-       epdv = ((pllmr & 0x00001800) >> 13) + 2;
+       if (fbdv == 0)
+               fbdv = 16;
+       cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
+       opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
+       ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
+       epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
        udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
 
-       m = fwdv * fbdv * cbdv;
+       /* check for 405GPr */
+       if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
+               fwdvb = 8 - (pllmr & 0x00000007);
+               if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
+                       if (psr & 0x00000020) /* New mode enable */
+                               m = fwdvb * 2 * ppdv;
+                       else
+                               m = fwdvb * cbdv * ppdv;
+               else if (psr & 0x00000020) /* New mode enable */
+                       if (psr & 0x00000800) /* PerClk synch mode */
+                               m = fwdvb * 2 * epdv;
+                       else
+                               m = fbdv * fwdv;
+               else if (epdv == fbdv)
+                       m = fbdv * cbdv * epdv;
+               else
+                       m = fbdv * fwdvb * cbdv;
 
-       cpu = sys_clk * m / fwdv;
-       plb = cpu / cbdv;
+               cpu = sys_clk * m / fwdv;
+               plb = sys_clk * m / (fwdvb * cbdv);
+       } else {
+               m = fwdv * fbdv * cbdv;
+               cpu = sys_clk * m / fwdv;
+               plb = cpu / cbdv;
+       }
        opb = plb / opdv;
        ebc = plb / epdv;
 
-       if (cpc0_cr0 & 0x80) {
+       if (cpc0_cr0 & 0x80)
                /* uart0 uses the external clock */
                uart0 = ser_clk;
-       } else {
+       else
                uart0 = cpu / udiv;
-       }
 
-       if (cpc0_cr0 & 0x40) {
+       if (cpc0_cr0 & 0x40)
                /* uart1 uses the external clock */
                uart1 = ser_clk;
-       } else {
+       else
                uart1 = cpu / udiv;
-       }
 
        /* setup the timebase clock to tick at the cpu frequency */
        cpc0_cr1 = cpc0_cr1 & ~0x00800000;
@@ -542,3 +587,45 @@ void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
        dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
 }
 
+
+void ibm405ep_fixup_clocks(unsigned int sys_clk)
+{
+       u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
+       u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
+       u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
+       u32 cpu, plb, opb, ebc, uart0, uart1;
+       u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
+       u32 pllmr0_ccdv, tb, m;
+
+       fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
+       fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
+       fbdv = (pllmr1 & 0x00f00000) >> 20;
+       if (fbdv == 0)
+               fbdv = 16;
+
+       cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
+       epdv = ((pllmr0 & 0x00000300) >> 8) + 2;  /* PLB:EBC */
+       opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
+
+       m = fbdv * fwdvb;
+
+       pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
+       if (pllmr1 & 0x80000000)
+               cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
+       else
+               cpu = sys_clk / pllmr0_ccdv;
+
+       plb = cpu / cbdv;
+       opb = plb / opdv;
+       ebc = plb / epdv;
+       tb = cpu;
+       uart0 = cpu / (cpc0_ucr & 0x0000007f);
+       uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
+
+       dt_fixup_cpu_clocks(cpu, tb, 0);
+       dt_fixup_clock("/plb", plb);
+       dt_fixup_clock("/plb/opb", opb);
+       dt_fixup_clock("/plb/ebc", ebc);
+       dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
+       dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
+}