#define M_PERFCTL_SUPERVISOR (1UL << 2)
#define M_PERFCTL_USER (1UL << 3)
#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
-#define M_PERFCTL_EVENT(event) ((event) << 5)
+#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5)
#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
#define M_COUNTER_OVERFLOW (1UL << 31)
#ifdef CONFIG_MIPS_MT_SMP
-#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
+#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
+#define vpe_id() smp_processor_id()
#else
-#define WHAT 0
+#define WHAT 0
+#define vpe_id() 0
#endif
#define __define_perf_accessors(r, n, np) \
\
static inline unsigned int r_c0_ ## r ## n(void) \
{ \
- unsigned int cpu = smp_processor_id(); \
+ unsigned int cpu = vpe_id(); \
\
switch (cpu) { \
case 0: \
\
static inline void w_c0_ ## r ## n(unsigned int value) \
{ \
- unsigned int cpu = smp_processor_id(); \
+ unsigned int cpu = vpe_id(); \
\
switch (cpu) { \
case 0: \
__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
-__define_perf_accessors(perfcntr, 2, 2)
-__define_perf_accessors(perfcntr, 3, 2)
+__define_perf_accessors(perfcntr, 2, 0)
+__define_perf_accessors(perfcntr, 3, 1)
__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
-__define_perf_accessors(perfctrl, 2, 2)
-__define_perf_accessors(perfctrl, 3, 2)
+__define_perf_accessors(perfctrl, 2, 0)
+__define_perf_accessors(perfctrl, 3, 1)
struct op_mips_model op_model_mipsxx_ops;
int i;
/* Compute the performance counter control word. */
- /* For now count kernel and user mode */
for (i = 0; i < counters; i++) {
reg.control[i] = 0;
reg.counter[i] = 0;
static inline int n_counters(void)
{
- int counters = __n_counters();
+ int counters;
-#ifndef CONFIG_SMP
- if (current_cpu_data.cputype == CPU_34K)
- return counters >> 1;
-#endif
+ switch (current_cpu_data.cputype) {
+ case CPU_R10000:
+ counters = 2;
+ break;
+
+ case CPU_R12000:
+ case CPU_R14000:
+ counters = 4;
+ break;
+
+ default:
+ counters = __n_counters();
+ }
return counters;
}
reset_counters(counters);
+#ifdef CONFIG_MIPS_MT_SMP
+ counters >>= 1;
+#endif
+
op_model_mipsxx_ops.num_counters = counters;
switch (current_cpu_data.cputype) {
case CPU_20KC:
op_model_mipsxx_ops.cpu_type = "mips/5K";
break;
+ case CPU_R10000:
+ if ((current_cpu_data.processor_id & 0xff) == 0x20)
+ op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
+ else
+ op_model_mipsxx_ops.cpu_type = "mips/r10000";
+ break;
+
+ case CPU_R12000:
+ case CPU_R14000:
+ op_model_mipsxx_ops.cpu_type = "mips/r12000";
+ break;
+
case CPU_SB1:
case CPU_SB1A:
op_model_mipsxx_ops.cpu_type = "mips/sb1";
static void mipsxx_exit(void)
{
- reset_counters(op_model_mipsxx_ops.num_counters);
+ int counters = op_model_mipsxx_ops.num_counters;
+#ifdef CONFIG_MIPS_MT_SMP
+ counters <<= 1;
+#endif
+ reset_counters(counters);
perf_irq = null_perf_irq;
}