[MIPS] Replace board_timer_setup function pointer by plat_timer_setup.

[pandora-kernel.git] / arch / mips / momentum / ocelot_3 / setup.c

diff --git a/arch/mips/momentum/ocelot_3/setup.c b/arch/mips/momentum/ocelot_3/setup.c
index 370e75d..435d078 100644 (file)
--- a/arch/mips/momentum/ocelot_3/setup.c
+++ b/arch/mips/momentum/ocelot_3/setup.c
@@ -197,7 +197,7 @@ int m48t37y_set_time(unsigned long sec)
        return 0;
 }
 
-void momenco_timer_setup(struct irqaction *irq)
+void __init plat_timer_setup(struct irqaction *irq)
 {
        setup_irq(7, irq);      /* Timer interrupt, unmask status IM7 */
 }
@@ -211,7 +211,6 @@ void momenco_time_init(void)
         * the Rm7900 and the Rm7065C
         */
        mips_hpt_frequency = cpu_clock / 2;
-       board_timer_setup = momenco_timer_setup;
 
        rtc_mips_get_time = m48t37y_get_time;
        rtc_mips_set_time = m48t37y_set_time;
@@ -313,7 +312,7 @@ static __init int __init ja_pci_init(void)
 
 arch_initcall(ja_pci_init);
 
-void __init plat_setup(void)
+void __init plat_mem_setup(void)
 {
        unsigned int tmpword;
 
@@ -329,22 +328,22 @@ void __init plat_setup(void)
        /* shut down ethernet ports, just to be sure our memory doesn't get
         * corrupted by random ethernet traffic.
         */
-       MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
-       MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
-       MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
-       MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
+       MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
+       MV_WRITE(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
+       MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
+       MV_WRITE(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
        do {}
-         while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
+         while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
        do {}
-         while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
+         while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
        do {}
-         while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
+         while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
        do {}
-         while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
-       MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
-                MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
-       MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
-                MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
+         while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
+       MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0),
+                MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
+       MV_WRITE(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1),
+                MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
 
        /* Turn off the Bit-Error LED */
        OCELOT_FPGA_WRITE(0x80, CLR);