Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart

[pandora-kernel.git] / arch / mips / mips-boards / generic / time.c

diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 6f8a9fe..a3c3a1d 100644 (file)
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -47,6 +47,9 @@
 #ifdef CONFIG_MIPS_MALTA
 #include <asm/mips-boards/maltaint.h>
 #endif
+#ifdef CONFIG_MIPS_SEAD
+#include <asm/mips-boards/seadint.h>
+#endif
 
 unsigned long cpu_khz;
 
@@ -187,7 +190,7 @@ out:
 }
 
 /*
- * Estimate CPU frequency.  Sets mips_counter_frequency as a side-effect
+ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  */
 static unsigned int __init estimate_cpu_frequency(void)
 {
@@ -208,7 +211,8 @@ static unsigned int __init estimate_cpu_frequency(void)
                count = 6000000;
 #endif
 #if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
-       unsigned int flags;
+       unsigned long flags;
+       unsigned int start;
 
        local_irq_save(flags);
 
@@ -217,13 +221,13 @@ static unsigned int __init estimate_cpu_frequency(void)
        while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
        /* Start r4k counter. */
-       write_c0_count(0);
+       start = read_c0_count();
 
        /* Read counter exactly on falling edge of update flag */
        while (CMOS_READ(RTC_REG_A) & RTC_UIP);
        while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
 
-       count = read_c0_count();
+       count = read_c0_count() - start;
 
        /* restore interrupts */
        local_irq_restore(flags);
@@ -262,11 +266,13 @@ void __init mips_time_init(void)
 
 void __init plat_timer_setup(struct irqaction *irq)
 {
+#ifdef MSC01E_INT_BASE
        if (cpu_has_veic) {
                set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
                mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
-       }
-       else {
+       } else
+#endif
+       {
                if (cpu_has_vint)
                        set_vi_handler (MIPSCPU_INT_CPUCTR, mips_timer_dispatch);
                mips_cpu_timer_irq = MIPSCPU_INT_BASE + MIPSCPU_INT_CPUCTR;
@@ -287,6 +293,7 @@ void __init plat_timer_setup(struct irqaction *irq)
           The effect is that the int remains disabled on the second cpu.
           Mark the interrupt with IRQ_PER_CPU to avoid any confusion */
        irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
+       set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
         /* to generate the first timer interrupt */