ret = -EIO;
if (copied != sizeof(tmp))
break;
- ret = put_user(tmp, (unsigned int *) (unsigned long) data);
+ ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
break;
}
break;
case FPC_EIR: { /* implementation / version register */
unsigned int flags;
+#ifdef CONFIG_MIPS_MT_SMTC
+ unsigned int irqflags;
+ unsigned int mtflags;
+#endif /* CONFIG_MIPS_MT_SMTC */
- if (!cpu_has_fpu)
+ if (!cpu_has_fpu) {
+ tmp = 0;
break;
+ }
+
+#ifdef CONFIG_MIPS_MT_SMTC
+ /* Read-modify-write of Status must be atomic */
+ local_irq_save(irqflags);
+ mtflags = dmt();
+#endif /* CONFIG_MIPS_MT_SMTC */
preempt_disable();
if (cpu_has_mipsmt) {
__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
write_c0_status(flags);
}
+#ifdef CONFIG_MIPS_MT_SMTC
+ emt(mtflags);
+ local_irq_restore(irqflags);
+#endif /* CONFIG_MIPS_MT_SMTC */
preempt_enable();
break;
}
- case DSP_BASE ... DSP_BASE + 5:
+ case DSP_BASE ... DSP_BASE + 5: {
+ dspreg_t *dregs;
+
if (!cpu_has_dsp) {
tmp = 0;
ret = -EIO;
goto out_tsk;
}
- dspreg_t *dregs = __get_dsp_regs(child);
+ dregs = __get_dsp_regs(child);
tmp = (unsigned long) (dregs[addr - DSP_BASE]);
break;
+ }
case DSP_CONTROL:
if (!cpu_has_dsp) {
tmp = 0;
ret = -EIO;
goto out_tsk;
}
- ret = put_user(tmp, (unsigned *) (unsigned long) data);
+ ret = put_user(tmp, (unsigned __user *) (unsigned long) data);
break;
}
else
child->thread.fpu.soft.fcr31 = data;
break;
- case DSP_BASE ... DSP_BASE + 5:
+ case DSP_BASE ... DSP_BASE + 5: {
+ dspreg_t *dregs;
+
if (!cpu_has_dsp) {
ret = -EIO;
break;
}
- dspreg_t *dregs = __get_dsp_regs(child);
+ dregs = __get_dsp_regs(child);
dregs[addr - DSP_BASE] = data;
break;
+ }
case DSP_CONTROL:
if (!cpu_has_dsp) {
ret = -EIO;