Pull asus into release branch

[pandora-kernel.git] / arch / mips / emma2rh / markeins / irq.c

diff --git a/arch/mips/emma2rh/markeins/irq.c b/arch/mips/emma2rh/markeins/irq.c
index 2a736be..6bcf6a0 100644 (file)
--- a/arch/mips/emma2rh/markeins/irq.c
+++ b/arch/mips/emma2rh/markeins/irq.c
@@ -29,7 +29,6 @@
 #include <linux/ptrace.h>
 #include <linux/delay.h>
 
-#include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/system.h>
 #include <asm/mipsregs.h>
@@ -57,7 +56,7 @@
 extern void emma2rh_sw_irq_init(u32 base);
 extern void emma2rh_gpio_irq_init(u32 base);
 extern void emma2rh_irq_init(u32 base);
-extern asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs);
+extern void emma2rh_irq_dispatch(void);
 
 static struct irqaction irq_cascade = {
           .handler = no_action,
@@ -106,7 +105,7 @@ void __init arch_init_irq(void)
        emma2rh_irq_init(EMMA2RH_IRQ_BASE);
        emma2rh_sw_irq_init(EMMA2RH_SW_IRQ_BASE);
        emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE);
-       mips_cpu_irq_init(CPU_IRQ_BASE);
+       mips_cpu_irq_init();
 
        /* setup cascade interrupts */
        setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade);
@@ -114,20 +113,20 @@ void __init arch_init_irq(void)
        setup_irq(CPU_IRQ_BASE + CPU_EMMA2RH_CASCADE, &irq_cascade);
 }
 
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
-        unsigned int pending = read_c0_status() & read_c0_cause();
+        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 
        if (pending & STATUSF_IP7)
-               do_IRQ(CPU_IRQ_BASE + 7, regs);
+               do_IRQ(CPU_IRQ_BASE + 7);
        else if (pending & STATUSF_IP2)
-               emma2rh_irq_dispatch(regs);
+               emma2rh_irq_dispatch();
        else if (pending & STATUSF_IP1)
-               do_IRQ(CPU_IRQ_BASE + 1, regs);
+               do_IRQ(CPU_IRQ_BASE + 1);
        else if (pending & STATUSF_IP0)
-               do_IRQ(CPU_IRQ_BASE + 0, regs);
+               do_IRQ(CPU_IRQ_BASE + 0);
        else
-               spurious_interrupt(regs);
+               spurious_interrupt();
 }