comment "Core B Support"
config BF561_COREB
- bool "Enable Core B support"
+ bool "Enable Core B loader"
default y
-config BF561_COREB_RESET
- bool "Enable Core B reset support"
- default n
- help
- This requires code in the application that is loaded
- into Core B. In order to reset, the application needs
- to install an interrupt handler for Supplemental
- Interrupt 0, that sets RETI to 0xff600000 and writes
- bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0.
- This causes Core B to stall when Supplemental Interrupt
- 0 is set, and will reset PC to 0xff600000 when
- COREB_SRAM_INIT is cleared.
-
endif
comment "Interrupt Priority Assignment"
default 9
config IRQ_TIMER0
int "TIMER 0 Interrupt"
+ default 7 if TICKSOURCE_GPTMR0
default 8
config IRQ_TIMER1
int "TIMER 1 Interrupt"