Blackfin: unify core IRQ definitions

[pandora-kernel.git] / arch / blackfin / mach-bf527 / include / mach / irq.h

diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d925..555d42a 100644 (file)
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,39 +7,10 @@
 #ifndef _BF527_IRQ_H_
 #define _BF527_IRQ_H_
 
-/*
- * Interrupt source definitions
-       Event Source    Core Event Name
-       Core        Emulation               **
-       Events         (highest priority)  EMU         0
-       Reset                   RST         1
-       NMI                     NMI         2
-       Exception               EVX         3
-       Reserved                --          4
-       Hardware Error          IVHW        5
-       Core Timer              IVTMR       6 *
-
-       .....
-
-        Software Interrupt 1    IVG14       31
-        Software Interrupt 2    --
-        (lowest priority)  IVG15       32 *
-*/
+#include <mach-common/irq.h>
 
 #define NR_PERI_INTS    (2 * 32)
 
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                        0       /* Emulation */
-#define IRQ_RST                        1       /* reset */
-#define IRQ_NMI                        2       /* Non Maskable */
-#define IRQ_EVX                        3       /* Exception */
-#define IRQ_UNUSED             4       /* - unused interrupt */
-#define IRQ_HWERR              5       /* Hardware Error */
-#define IRQ_CORETMR            6       /* Core timer */
-
-#define BFIN_IRQ(x)            ((x) + 7)
-
 #define IRQ_PLL_WAKEUP         BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR         BFIN_IRQ(1)     /* DMA Error 0 (generic) */
 #define IRQ_DMAR0_BLK          BFIN_IRQ(2)     /* DMAR0 Block Interrupt */
@@ -161,17 +132,6 @@
 #define IRQ_MAC_STMDONE                126 /* Station Mgt. Transfer Done Interrupt */
 
 #define NR_MACH_IRQS   (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS                (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS     0