memcg: reduce size of mem_cgroup by using nr_cpu_ids

[pandora-kernel.git] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 19b43f3..a949c4f 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -26,6 +26,7 @@ config BLACKFIN
        default y
        select HAVE_IDE
        select HAVE_OPROFILE
+       select ARCH_WANT_OPTIONAL_GPIOLIB
 
 config ZONE_DMA
        bool
@@ -59,10 +60,6 @@ config GENERIC_CALIBRATE_DELAY
        bool
        default y
 
-config HARDWARE_PM
-       def_bool y
-       depends on OPROFILE
-
 source "init/Kconfig"
 
 source "kernel/Kconfig.preempt"
@@ -199,6 +196,32 @@ config BF561
 
 endchoice
 
+config SMP
+       depends on BF561
+       bool "Symmetric multi-processing support"
+       ---help---
+         This enables support for systems with more than one CPU,
+         like the dual core BF561. If you have a system with only one
+         CPU, say N. If you have a system with more than one CPU, say Y.
+
+         If you don't know what to do here, say N.
+
+config NR_CPUS
+       int
+       depends on SMP
+       default 2 if BF561
+
+config IRQ_PER_CPU
+       bool
+       depends on SMP
+       default y
+
+config TICK_SOURCE_SYSTMR0
+       bool
+       select BFIN_GPTIMERS
+       depends on SMP
+       default y
+
 config BF_REV_MIN
        int
        default 0 if (BF51x || BF52x || BF54x)
@@ -307,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75
        depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
        default y
 
+config MEM_MT48LC32M8A2_75
+       bool
+       depends on (BFIN518F_EZBRD)
+       default y
+
 source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
@@ -345,6 +373,7 @@ config BOOT_LOAD
 
 config ROM_BASE
        hex "Kernel ROM Base"
+       depends on ROMKERNEL
        default "0x20040000"
        range 0x20000000 0x20400000 if !(BF54x || BF561)
        range 0x20000000 0x30000000 if (BF54x || BF561)
@@ -445,13 +474,60 @@ config MEM_MT46V32M16_5B
        bool "MT46V32M16_5B"
 endchoice
 
-config MAX_MEM_SIZE
-       int "Max SDRAM Memory Size in MBytes"
-       depends on !MPU
-       default 512
+choice
+       prompt "DDR/SDRAM Timing"
+       depends on BFIN_KERNEL_CLOCK
+       default BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       help
+         This option allows you to specify Blackfin SDRAM/DDR Timing parameters
+         The calculated SDRAM timing parameters may not be 100%
+         accurate - This option is therefore marked experimental.
+
+config BFIN_KERNEL_CLOCK_MEMINIT_CALC
+       bool "Calculate Timings (EXPERIMENTAL)"
+       depends on EXPERIMENTAL
+
+config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+       bool "Provide accurate Timings based on target SCLK"
        help
-         This is the max memory size that the kernel will create CPLB
-         tables for.  Your system will not be able to handle any more.
+         Please consult the Blackfin Hardware Reference Manuals as well
+         as the memory device datasheet.
+         http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+endchoice
+
+menu "Memory Init Control"
+       depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
+
+config MEM_DDRCTL0
+       depends on BF54x
+       hex "DDRCTL0"
+       default 0x0
+
+config MEM_DDRCTL1
+       depends on BF54x
+       hex "DDRCTL1"
+       default 0x0
+
+config MEM_DDRCTL2
+       depends on BF54x
+       hex "DDRCTL2"
+       default 0x0
+
+config MEM_EBIU_DDRQUE
+       depends on BF54x
+       hex "DDRQUE"
+       default 0x0
+
+config MEM_SDRRC
+       depends on !BF54x
+       hex "SDRRC"
+       default 0x0
+
+config MEM_SDGCTL
+       depends on !BF54x
+       hex "SDGCTL"
+       default 0x0
+endmenu
 
 #
 # Max & Min Speeds for various Chips
@@ -501,6 +577,7 @@ source kernel/Kconfig.hz
 
 config GENERIC_TIME
        bool "Generic time"
+       depends on !SMP
        default y
 
 config GENERIC_CLOCKEVENTS
@@ -575,6 +652,7 @@ endmenu
 
 
 menu "Blackfin Kernel Optimizations"
+       depends on !SMP
 
 comment "Memory Optimizations"
 
@@ -737,7 +815,6 @@ config BFIN_INS_LOWOVERHEAD
 
 endmenu
 
-
 choice
        prompt "Kernel executes from"
        help
@@ -767,16 +844,9 @@ config BFIN_GPTIMERS
          To compile this driver as a module, choose M here: the module
          will be called gptimers.ko.
 
-config BFIN_DMA_5XX
-       bool "Enable DMA Support"
-       default y
-       help
-         DMA driver for Blackfin parts.
-
 choice
        prompt "Uncached DMA region"
        default DMA_UNCACHED_1M
-       depends on BFIN_DMA_5XX
 config DMA_UNCACHED_4M
        bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M
@@ -803,9 +873,11 @@ config BFIN_ICACHE_LOCK
 choice
        prompt "Policy"
        depends on BFIN_DCACHE
-       default BFIN_WB
+       default BFIN_WB if !SMP
+       default BFIN_WT if SMP
 config BFIN_WB
        bool "Write back"
+       depends on !SMP
        help
          Write Back Policy:
            Cached data will be written back to SDRAM only when needed.
@@ -842,7 +914,7 @@ endchoice
 
 config BFIN_L2_CACHEABLE
        bool "Cache L2 SRAM"
-       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
        default n
        help
          Select to make L2 SRAM cacheable in L1 data and instruction cache.
@@ -1032,7 +1104,7 @@ config PM_WAKEUP_GPIO_NUMBER
        int "GPIO number"
        range 0 47
        depends on PM_WAKEUP_BY_GPIO
-       default 2 if BFIN537_STAMP
+       default 2
 
 choice
        prompt "GPIO Polarity"
@@ -1072,15 +1144,21 @@ menu "CPU Frequency scaling"
 
 source "drivers/cpufreq/Kconfig"
 
+config BFIN_CPU_FREQ
+       bool
+       depends on CPU_FREQ
+       select CPU_FREQ_TABLE
+       default y
+
 config CPU_VOLTAGE
        bool "CPU Voltage scaling"
-       depends on EXPERIMENTAL 
+       depends on EXPERIMENTAL
        depends on CPU_FREQ
        default n
        help
          Say Y here if you want CPU voltage scaling according to the CPU frequency.
          This option violates the PLL BYPASS recommendation in the Blackfin Processor
-         manuals. There is a theoretical risk that during VDDINT transitions 
+         manuals. There is a theoretical risk that during VDDINT transitions
          the PLL may unlock.
 
 endmenu