#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
#define OMAP24XX_GPIO_RISINGDETECT 0x0048
#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
+#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
+#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
void omap_set_gpio_direction(int gpio, int is_input)
{
struct gpio_bank *bank;
+ unsigned long flags;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
}
static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
void omap_set_gpio_dataout(int gpio, int enable)
{
struct gpio_bank *bank;
+ unsigned long flags;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
}
int omap_get_gpio_datain(int gpio)
__raw_writel(l, base + reg); \
} while(0)
+void omap_set_gpio_debounce(int gpio, int enable)
+{
+ struct gpio_bank *bank;
+ void __iomem *reg;
+ u32 val, l = 1 << get_gpio_index(gpio);
+
+ if (cpu_class_is_omap1())
+ return;
+
+ bank = get_gpio_bank(gpio);
+ reg = bank->base;
+
+ reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+ val = __raw_readl(reg);
+
+ if (enable)
+ val |= l;
+ else
+ val &= ~l;
+
+ __raw_writel(val, reg);
+}
+EXPORT_SYMBOL(omap_set_gpio_debounce);
+
+void omap_set_gpio_debounce_time(int gpio, int enc_time)
+{
+ struct gpio_bank *bank;
+ void __iomem *reg;
+
+ if (cpu_class_is_omap1())
+ return;
+
+ bank = get_gpio_bank(gpio);
+ reg = bank->base;
+
+ enc_time &= 0xff;
+ reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+ __raw_writel(enc_time, reg);
+}
+EXPORT_SYMBOL(omap_set_gpio_debounce_time);
+
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
+static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+ int trigger)
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
trigger & __IRQT_RISEDGE);
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
trigger & __IRQT_FALEDGE);
+
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (trigger != 0)
- __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
+ __raw_writel(1 << gpio, bank->base
+ + OMAP24XX_GPIO_SETWKUENA);
else
- __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
+ __raw_writel(1 << gpio, bank->base
+ + OMAP24XX_GPIO_CLEARWKUENA);
} else {
if (trigger != 0)
bank->enabled_non_wakeup_gpios |= gpio_bit;
else
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
}
- /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
- * triggering requested. */
+
+ /*
+ * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
+ * level triggering requested.
+ */
}
#endif
struct gpio_bank *bank;
unsigned gpio;
int retval;
+ unsigned long flags;
if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
return -EINVAL;
bank = get_irq_chip_data(irq);
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
if (retval == 0) {
irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
irq_desc[irq].status |= type;
}
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return retval;
}
*/
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
{
+ unsigned long flags;
+
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP16XX
case METHOD_MPUIO:
case METHOD_GPIO_1610:
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
if (enable) {
bank->suspend_wakeup |= (1 << gpio);
enable_irq_wake(bank->irq);
disable_irq_wake(bank->irq);
bank->suspend_wakeup &= ~(1 << gpio);
}
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
(bank - gpio_bank) * 32 + gpio);
return -EINVAL;
}
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
if (enable) {
bank->suspend_wakeup |= (1 << gpio);
enable_irq_wake(bank->irq);
disable_irq_wake(bank->irq);
bank->suspend_wakeup &= ~(1 << gpio);
}
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
#endif
default:
int omap_request_gpio(int gpio)
{
struct gpio_bank *bank;
+ unsigned long flags;
if (check_gpio(gpio) < 0)
return -EINVAL;
bank = get_gpio_bank(gpio);
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
dump_stack();
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return -1;
}
bank->reserved_map |= (1 << get_gpio_index(gpio));
__raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
}
#endif
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
void omap_free_gpio(int gpio)
{
struct gpio_bank *bank;
+ unsigned long flags;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
dump_stack();
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return;
}
#ifdef CONFIG_ARCH_OMAP16XX
#endif
bank->reserved_map &= ~(1 << get_gpio_index(gpio));
_reset_gpio(bank, gpio);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
}
/*
static void gpio_unmask_irq(unsigned int irq)
{
unsigned int gpio = irq - IH_GPIO_BASE;
- unsigned int gpio_idx = get_gpio_index(gpio);
struct gpio_bank *bank = get_irq_chip_data(irq);
- _set_gpio_irqenable(bank, gpio_idx, 1);
+ _set_gpio_irqenable(bank, gpio, 1);
}
static struct irq_chip gpio_irq_chip = {
{
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ unsigned long flags;
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
bank->saved_wakeup = __raw_readl(mask_reg);
__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
{
struct gpio_bank *bank = platform_get_drvdata(pdev);
void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+ unsigned long flags;
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
__raw_writel(bank->saved_wakeup, mask_reg);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
#endif
+/* This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
static int __init _omap_gpio_init(void)
{
int i;
#endif
for (j = bank->virtual_irq_start;
j < bank->virtual_irq_start + gpio_count; j++) {
+ lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
set_irq_chip_data(j, bank);
if (bank_is_mpuio(bank))
set_irq_chip(j, &mpuio_irq_chip);
void __iomem *wake_status;
void __iomem *wake_clear;
void __iomem *wake_set;
+ unsigned long flags;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP16XX
continue;
}
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
bank->saved_wakeup = __raw_readl(wake_status);
__raw_writel(0xffffffff, wake_clear);
__raw_writel(bank->suspend_wakeup, wake_set);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
}
return 0;
struct gpio_bank *bank = &gpio_bank[i];
void __iomem *wake_clear;
void __iomem *wake_set;
+ unsigned long flags;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP16XX
continue;
}
- spin_lock(&bank->lock);
+ spin_lock_irqsave(&bank->lock, flags);
__raw_writel(0xffffffff, wake_clear);
__raw_writel(bank->saved_wakeup, wake_set);
- spin_unlock(&bank->lock);
+ spin_unlock_irqrestore(&bank->lock, flags);
}
return 0;
git.openpandora.org / pandora-kernel.git / blobdiff