Merge branch 'usb-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

[pandora-kernel.git] / arch / arm / plat-mxc / avic.c

diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55d2534..55f1569 100644 (file)
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <mach/common.h>
 #include <asm/mach/irq.h>
+#include <asm/exception.h>
 #include <mach/hardware.h>
 
 #include "irq-common.h"
@@ -50,6 +51,8 @@
 
 void __iomem *avic_base;
 
+static u32 avic_saved_mask_reg[2];
+
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -90,24 +93,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 }
 #endif /* CONFIG_FIQ */
 
-/* Disable interrupt number "irq" in the AVIC */
-static void mxc_mask_irq(struct irq_data *d)
-{
-       __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
-}
 
-/* Enable interrupt number "irq" in the AVIC */
-static void mxc_unmask_irq(struct irq_data *d)
-{
-       __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
-}
-
-static struct mxc_irq_chip mxc_avic_chip = {
-       .base = {
-               .irq_ack = mxc_mask_irq,
-               .irq_mask = mxc_mask_irq,
-               .irq_unmask = mxc_unmask_irq,
-       },
+static struct mxc_extra_irq avic_extra_irq = {
 #ifdef CONFIG_MXC_IRQ_PRIOR
        .set_priority = avic_irq_set_priority,
 #endif
@@ -116,6 +103,68 @@ static struct mxc_irq_chip mxc_avic_chip = {
 #endif
 };
 
+#ifdef CONFIG_PM
+static void avic_irq_suspend(struct irq_data *d)
+{
+       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+       struct irq_chip_type *ct = gc->chip_types;
+       int idx = gc->irq_base >> 5;
+
+       avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
+       __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
+}
+
+static void avic_irq_resume(struct irq_data *d)
+{
+       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+       struct irq_chip_type *ct = gc->chip_types;
+       int idx = gc->irq_base >> 5;
+
+       __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+}
+
+#else
+#define avic_irq_suspend NULL
+#define avic_irq_resume NULL
+#endif
+
+static __init void avic_init_gc(unsigned int irq_start)
+{
+       struct irq_chip_generic *gc;
+       struct irq_chip_type *ct;
+       int idx = irq_start >> 5;
+
+       gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
+                                   handle_level_irq);
+       gc->private = &avic_extra_irq;
+       gc->wake_enabled = IRQ_MSK(32);
+
+       ct = gc->chip_types;
+       ct->chip.irq_mask = irq_gc_mask_clr_bit;
+       ct->chip.irq_unmask = irq_gc_mask_set_bit;
+       ct->chip.irq_ack = irq_gc_mask_clr_bit;
+       ct->chip.irq_set_wake = irq_gc_set_wake;
+       ct->chip.irq_suspend = avic_irq_suspend;
+       ct->chip.irq_resume = avic_irq_resume;
+       ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
+       ct->regs.ack = ct->regs.mask;
+
+       irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
+}
+
+asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+{
+       u32 nivector;
+
+       do {
+               nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+               if (nivector == 0xffff)
+                       break;
+
+               handle_IRQ(nivector, regs);
+       } while (1);
+}
+
 /*
  * This function initializes the AVIC hardware and disables all the
  * interrupts. It registers the interrupt enable and disable functions
@@ -140,11 +189,9 @@ void __init mxc_init_irq(void __iomem *irqbase)
        /* all IRQ no FIQ */
        __raw_writel(0, avic_base + AVIC_INTTYPEH);
        __raw_writel(0, avic_base + AVIC_INTTYPEL);
-       for (i = 0; i < AVIC_NUM_IRQS; i++) {
-               irq_set_chip_and_handler(i, &mxc_avic_chip.base,
-                                        handle_level_irq);
-               set_irq_flags(i, IRQF_VALID);
-       }
+
+       for (i = 0; i < AVIC_NUM_IRQS; i += 32)
+               avic_init_gc(i);
 
        /* Set default priority value (0) for all IRQ's */
        for (i = 0; i < 8; i++)
@@ -157,4 +204,3 @@ void __init mxc_init_irq(void __iomem *irqbase)
 
        printk(KERN_INFO "MXC IRQ initialized\n");
 }
-