ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+

[pandora-kernel.git] / arch / arm / mm / proc-xsc3.S

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index dc16458..f8acdfe 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -83,7 +83,7 @@
  * Nothing too exciting at the moment
  */
 ENTRY(cpu_xsc3_proc_init)
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_xsc3_proc_fin()
@@ -93,7 +93,7 @@ ENTRY(cpu_xsc3_proc_fin)
        bic     r0, r0, #0x1800                 @ ...IZ...........
        bic     r0, r0, #0x0006                 @ .............CA.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_xsc3_reset(loc)
@@ -119,7 +119,7 @@ ENTRY(cpu_xsc3_reset)
        @ CAUTION: MMU turned off from this point.  We count on the pipeline
        @ already containing those two last instructions to survive.
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I and D TLBs
-       mov     pc, r0
+       ret     r0
 ENDPROC(cpu_xsc3_reset)
        .popsection
 
@@ -138,7 +138,7 @@ ENDPROC(cpu_xsc3_reset)
 ENTRY(cpu_xsc3_do_idle)
        mov     r0, #1
        mcr     p14, 0, r0, c7, c0, 0           @ go to idle
-       mov     pc, lr
+       ret     lr
 
 /* ================================= CACHE ================================ */
 
@@ -150,7 +150,7 @@ ENTRY(cpu_xsc3_do_idle)
 ENTRY(xsc3_flush_icache_all)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-       mov     pc, lr
+       ret     lr
 ENDPROC(xsc3_flush_icache_all)
 
 /*
@@ -176,7 +176,7 @@ __flush_whole_cache:
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate L1 I cache and BTB
        mcrne   p15, 0, ip, c7, c10, 4          @ data write barrier
        mcrne   p15, 0, ip, c7, c5, 4           @ prefetch flush
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_user_cache_range(start, end, vm_flags)
@@ -205,7 +205,7 @@ ENTRY(xsc3_flush_user_cache_range)
        mcrne   p15, 0, ip, c7, c5, 6           @ invalidate BTB
        mcrne   p15, 0, ip, c7, c10, 4          @ data write barrier
        mcrne   p15, 0, ip, c7, c5, 4           @ prefetch flush
-       mov     pc, lr
+       ret     lr
 
 /*
  *     coherent_kern_range(start, end)
@@ -232,7 +232,7 @@ ENTRY(xsc3_coherent_user_range)
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate L1 I cache and BTB
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
        mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_kern_dcache_area(void *addr, size_t size)
@@ -253,7 +253,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate L1 I cache and BTB
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
        mcr     p15, 0, r0, c7, c5, 4           @ prefetch flush
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_inv_range(start, end)
@@ -277,7 +277,7 @@ xsc3_dma_inv_range:
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_clean_range(start, end)
@@ -294,7 +294,7 @@ xsc3_dma_clean_range:
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_flush_range(start, end)
@@ -311,7 +311,7 @@ ENTRY(xsc3_dma_flush_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_map_area(start, size, dir)
@@ -334,7 +334,7 @@ ENDPROC(xsc3_dma_map_area)
  *     - dir   - DMA direction
  */
 ENTRY(xsc3_dma_unmap_area)
-       mov     pc, lr
+       ret     lr
 ENDPROC(xsc3_dma_unmap_area)
 
        .globl  xsc3_flush_kern_cache_louis
@@ -348,7 +348,7 @@ ENTRY(cpu_xsc3_dcache_clean_area)
        add     r0, r0, #CACHELINESIZE
        subs    r1, r1, #CACHELINESIZE
        bhi     1b
-       mov     pc, lr
+       ret     lr
 
 /* =============================== PageTable ============================== */
 
@@ -406,7 +406,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
        orr     r2, r2, ip
 
        xscale_set_pte_ext_epilogue
-       mov     pc, lr
+       ret     lr
 
        .ltorg
        .align
@@ -478,7 +478,7 @@ __xsc3_setup:
        bic     r0, r0, r5                      @ ..V. ..R. .... ..A.
        orr     r0, r0, r6                      @ ..VI Z..S .... .C.M (mmu)
                                                @ ...I Z..S .... .... (uc)
-       mov     pc, lr
+       ret     lr
 
        .size   __xsc3_setup, . - __xsc3_setup