ARM: pm: only use preallocated page table during resume

[pandora-kernel.git] / arch / arm / mm / proc-arm926.S

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 48add84..9f8fd91 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -394,27 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext)
 
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl cpu_arm926_suspend_size
-.equ   cpu_arm926_suspend_size, 4 * 4
+.equ   cpu_arm926_suspend_size, 4 * 3
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_arm926_do_suspend)
-       stmfd   sp!, {r4 - r7, lr}
+       stmfd   sp!, {r4 - r6, lr}
        mrc     p15, 0, r4, c13, c0, 0  @ PID
        mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
-       mrc     p15, 0, r6, c2, c0, 0   @ TTB address
-       mrc     p15, 0, r7, c1, c0, 0   @ Control register
-       stmia   r0, {r4 - r7}
-       ldmfd   sp!, {r4 - r7, pc}
+       mrc     p15, 0, r6, c1, c0, 0   @ Control register
+       stmia   r0, {r4 - r6}
+       ldmfd   sp!, {r4 - r6, pc}
 ENDPROC(cpu_arm926_do_suspend)
 
 ENTRY(cpu_arm926_do_resume)
        mov     ip, #0
        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I+D TLBs
        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I+D caches
-       ldmia   r0, {r4 - r7}
+       ldmia   r0, {r4 - r6}
        mcr     p15, 0, r4, c13, c0, 0  @ PID
        mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
-       mcr     p15, 0, r6, c2, c0, 0   @ TTB address
-       mov     r0, r7                  @ control register
+       mcr     p15, 0, r1, c2, c0, 0   @ TTB address
+       mov     r0, r6                  @ control register
        b       cpu_resume_mmu
 ENDPROC(cpu_arm926_do_resume)
 #endif