ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+

[pandora-kernel.git] / arch / arm / mm / proc-arm1026.S

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 4799a24..fc29406 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -62,7 +62,7 @@
  * cpu_arm1026_proc_init()
  */
 ENTRY(cpu_arm1026_proc_init)
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_arm1026_proc_fin()
@@ -72,7 +72,7 @@ ENTRY(cpu_arm1026_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_arm1026_reset(loc)
@@ -96,7 +96,7 @@ ENTRY(cpu_arm1026_reset)
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-       mov     pc, r0
+       ret     r0
 ENDPROC(cpu_arm1026_reset)
        .popsection
 
@@ -106,7 +106,7 @@ ENDPROC(cpu_arm1026_reset)
        .align  5
 ENTRY(cpu_arm1026_do_idle)
        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
-       mov     pc, lr
+       ret     lr
 
 /* ================================= CACHE ================================ */
 
@@ -122,7 +122,7 @@ ENTRY(arm1026_flush_icache_all)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
 #endif
-       mov     pc, lr
+       ret     lr
 ENDPROC(arm1026_flush_icache_all)
 
 /*
@@ -151,7 +151,7 @@ __flush_whole_cache:
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 #endif
        mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_user_cache_range(start, end, flags)
@@ -180,7 +180,7 @@ ENTRY(arm1026_flush_user_cache_range)
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 #endif
        mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     coherent_kern_range(start, end)
@@ -219,7 +219,7 @@ ENTRY(arm1026_coherent_user_range)
        blo     1b
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     r0, #0
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_kern_dcache_area(void *addr, size_t size)
@@ -240,7 +240,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
        blo     1b
 #endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_inv_range(start, end)
@@ -269,7 +269,7 @@ arm1026_dma_inv_range:
        blo     1b
 #endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_clean_range(start, end)
@@ -291,7 +291,7 @@ arm1026_dma_clean_range:
        blo     1b
 #endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_flush_range(start, end)
@@ -311,7 +311,7 @@ ENTRY(arm1026_dma_flush_range)
        blo     1b
 #endif
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_map_area(start, size, dir)
@@ -334,7 +334,7 @@ ENDPROC(arm1026_dma_map_area)
  *     - dir   - DMA direction
  */
 ENTRY(arm1026_dma_unmap_area)
-       mov     pc, lr
+       ret     lr
 ENDPROC(arm1026_dma_unmap_area)
 
        .globl  arm1026_flush_kern_cache_louis
@@ -352,7 +352,7 @@ ENTRY(cpu_arm1026_dcache_clean_area)
        subs    r1, r1, #CACHE_DLINESIZE
        bhi     1b
 #endif
-       mov     pc, lr
+       ret     lr
 
 /* =============================== PageTable ============================== */
 
@@ -378,7 +378,7 @@ ENTRY(cpu_arm1026_switch_mm)
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 #endif
-       mov     pc, lr
+       ret     lr
         
 /*
  * cpu_arm1026_set_pte_ext(ptep, pte, ext)
@@ -394,7 +394,7 @@ ENTRY(cpu_arm1026_set_pte_ext)
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 #endif
 #endif /* CONFIG_MMU */
-       mov     pc, lr
+       ret     lr
 
        .type   __arm1026_setup, #function
 __arm1026_setup:
@@ -417,7 +417,7 @@ __arm1026_setup:
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
-       mov     pc, lr
+       ret     lr
        .size   __arm1026_setup, . - __arm1026_setup
 
        /*