ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5

[pandora-kernel.git] / arch / arm / mm / abort-ev6.S

diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 1478aa5..52db4a3 100644 (file)
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,8 +4,8 @@
 /*
  * Function: v6_early_abort
  *
- * Params  : r2 = address of aborted instruction
- *         : r3 = saved SPSR
+ * Params  : r4 = aborted context pc
+ *        : r5 = aborted context psr
  *
  * Returns : r0 = address of abort
  *        : r1 = FSR, bit 11 = write
@@ -33,16 +33,14 @@ ENTRY(v6_early_abort)
  * The test below covers all the write situations, including Java bytecodes
  */
        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
-       tst     r3, #PSR_J_BIT                  @ Java?
+       tst     r5, #PSR_J_BIT                  @ Java?
        movne   pc, lr
-       do_thumb_abort
-       ldreq   r3, [r2]                        @ read aborted ARM instruction
+       do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+       ldreq   r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
        reveq   r3, r3
 #endif
-       do_ldrd_abort
+       do_ldrd_abort tmp=r2, insn=r3
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
        mov     pc, lr
-
-