ARM: use generic ioremap_page_range()

[pandora-kernel.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5bd7c89..87ec141 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -572,6 +572,8 @@ config CPU_TLB_V6
 config CPU_TLB_V7
        bool
 
+config VERIFY_PERMISSION_FAULT
+       bool
 endif
 
 config CPU_HAS_ASID
@@ -715,17 +717,6 @@ config TLS_REG_EMUL
          a few prototypes like that in existence) and therefore access to
          that required register must be emulated.
 
-config HAS_TLS_REG
-       bool
-       depends on !TLS_REG_EMUL
-       default y if SMP || CPU_32v7
-       help
-         This selects support for the CP15 thread register.
-         It is defined to be available on some ARMv6 processors (including
-         all SMP capable ARMv6's) or later processors.  User space may
-         assume directly accessing that register and always obtain the
-         expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
        bool
        help
@@ -733,6 +724,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
          Forget about fast user space cmpxchg support.
          It is just not possible.
 
+config DMA_CACHE_RWFO
+       bool "Enable read/write for ownership DMA cache maintenance"
+       depends on CPU_V6 && SMP
+       default y
+       help
+         The Snoop Control Unit on ARM11MPCore does not detect the
+         cache maintenance operations and the dma_{map,unmap}_area()
+         functions may leave stale cache entries on other CPUs. By
+         enabling this option, Read or Write For Ownership in the ARMv6
+         DMA cache maintenance functions is performed. These LDR/STR
+         instructions change the cache line state to shared or modified
+         so that the cache operation has the desired effect.
+
+         Note that the workaround is only valid on processors that do
+         not perform speculative loads into the D-cache. For such
+         processors, if cache maintenance operations are not broadcast
+         in hardware, other workarounds are needed (e.g. cache
+         maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
        bool
 
@@ -760,7 +770,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
+                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
+                  ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
        default y
        select OUTER_CACHE
        select OUTER_CACHE_SYNC
@@ -769,7 +780,7 @@ config CACHE_L2X0
 
 config CACHE_TAUROS2
        bool "Enable the Tauros2 L2 cache controller"
-       depends on ARCH_DOVE
+       depends on (ARCH_DOVE || ARCH_MMP)
        default y
        select OUTER_CACHE
        help
@@ -789,6 +800,27 @@ config ARM_L1_CACHE_SHIFT
        default 6 if ARM_L1_CACHE_SHIFT_6
        default 5
 
+config ARM_DMA_MEM_BUFFERABLE
+       bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+       depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+                    MACH_REALVIEW_PB11MP)
+       default y if CPU_V6 || CPU_V7
+       help
+         Historically, the kernel has used strongly ordered mappings to
+         provide DMA coherent memory.  With the advent of ARMv7, mapping
+         memory with differing types results in unpredictable behaviour,
+         so on these CPUs, this option is forced on.
+
+         Multiple mappings with differing attributes is also unpredictable
+         on ARMv6 CPUs, but since they do not have aggressive speculative
+         prefetch, no harm appears to occur.
+
+         However, drivers may be missing the necessary barriers for ARMv6,
+         and therefore turning this on may result in unpredictable driver
+         behaviour.  Therefore, we offer this as an option.
+
+         You are recommended say 'Y' here and debug any affected drivers.
+
 config ARCH_HAS_BARRIERS
        bool
        help